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Filtros : "MICROELETRÔNICA" "Microelectronic Engineering" Removidos: "International Conference on Control Systems and Computer Science" "Micromachining Technology for Micro-Optics and Nano-Optics" Limpar

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  • Artigo de periodico

    In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs (2015)

    Doria, Rodrigo Trevisoli ; Claeys, Cor ; Simoen, Eddy ; Souza, Marcio Alves Sodré de; Martino, João Antonio

    Source: Microelectronic Engineering. Unidade: EP

    Assunto: MICROELETRÔNICA

    Acesso à fonteDOIHow to cite
    A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas

    • ABNT

      DORIA, Rodrigo Trevisoli et al. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs. Microelectronic Engineering, v. 147, n. 1, p. 92-95, 2015Tradução . . Disponível em: https://doi.org/10.1016/j.mee.2015.04.056. Acesso em: 11 nov. 2024.

    • APA

      Doria, R. T., Claeys, C., Simoen, E., Souza, M. A. S. de, & Martino, J. A. (2015). In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs. Microelectronic Engineering, 147( 1), 92-95. doi:10.1016/j.mee.2015.04.056

    • NLM

      Doria RT, Claeys C, Simoen E, Souza MAS de, Martino JA. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs [Internet]. Microelectronic Engineering. 2015 ; 147( 1): 92-95.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.mee.2015.04.056

    • Vancouver

      Doria RT, Claeys C, Simoen E, Souza MAS de, Martino JA. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs [Internet]. Microelectronic Engineering. 2015 ; 147( 1): 92-95.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/j.mee.2015.04.056

  • Artigo de periodico

    Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k (1997)

    Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre

    Source: Microelectronic Engineering. Unidade: EP

    Assunto: MICROELETRÔNICA

    Acesso à fonteDOIHow to cite
    A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas

    • ABNT

      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, v. 36, n. 1-4, p. 375-378, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0167-9317(97)00083-x. Acesso em: 11 nov. 2024.

    • APA

      Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, 36( 1-4), 375-378. doi:10.1016/s0167-9317(97)00083-x

    • NLM

      Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x

    • Vancouver

      Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2024 nov. 11 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x
  • 1

1 - 2 (2 records)

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