Filtros : "MICROELETRÔNICA" "Holanda" Removido: "Indexado no ASCA" Limpar

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  • Fonte: Microelectronics Journal. Unidade: EP

    Assuntos: NANOTECNOLOGIA, MICROELETRÔNICA, ELETROQUÍMICA

    Acesso à fonteDOIComo citar
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    • ABNT

      HUANCA, Danilo Roque e RAIMUNDO, Daniel Scodeler e SALCEDO, Walter Jaimes. Backside contact effect on the morphological and optical features of porous silicon photonic crystals. Microelectronics Journal, v. 40, n. 4-5, p. 744-748, 2009Tradução . . Disponível em: https://doi.org/10.1016/j.mejo.2008.11.005. Acesso em: 06 set. 2024.
    • APA

      Huanca, D. R., Raimundo, D. S., & Salcedo, W. J. (2009). Backside contact effect on the morphological and optical features of porous silicon photonic crystals. Microelectronics Journal, 40( 4-5), 744-748. doi:10.1016/j.mejo.2008.11.005
    • NLM

      Huanca DR, Raimundo DS, Salcedo WJ. Backside contact effect on the morphological and optical features of porous silicon photonic crystals [Internet]. Microelectronics Journal. 2009 ; 40( 4-5): 744-748.[citado 2024 set. 06 ] Available from: https://doi.org/10.1016/j.mejo.2008.11.005
    • Vancouver

      Huanca DR, Raimundo DS, Salcedo WJ. Backside contact effect on the morphological and optical features of porous silicon photonic crystals [Internet]. Microelectronics Journal. 2009 ; 40( 4-5): 744-748.[citado 2024 set. 06 ] Available from: https://doi.org/10.1016/j.mejo.2008.11.005
  • Fonte: Microelectronics Journal. Unidade: EP

    Assuntos: NANOTECNOLOGIA, MICROELETRÔNICA

    Acesso à fonteDOIComo citar
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    • ABNT

      RAIMUNDO, Daniel Scodeler et al. Anodic porous alumina structural characteristics study based on SEM image processing and analysis. Microelectronics Journal, v. 40, n. 4-5, p. 844-847, 2009Tradução . . Disponível em: https://doi.org/10.1016/j.mejo.2008.11.024. Acesso em: 06 set. 2024.
    • APA

      Raimundo, D. S., Calíope, P. B., Huanca, D. R., & Salcedo, W. J. (2009). Anodic porous alumina structural characteristics study based on SEM image processing and analysis. Microelectronics Journal, 40( 4-5), 844-847. doi:10.1016/j.mejo.2008.11.024
    • NLM

      Raimundo DS, Calíope PB, Huanca DR, Salcedo WJ. Anodic porous alumina structural characteristics study based on SEM image processing and analysis [Internet]. Microelectronics Journal. 2009 ; 40( 4-5): 844-847.[citado 2024 set. 06 ] Available from: https://doi.org/10.1016/j.mejo.2008.11.024
    • Vancouver

      Raimundo DS, Calíope PB, Huanca DR, Salcedo WJ. Anodic porous alumina structural characteristics study based on SEM image processing and analysis [Internet]. Microelectronics Journal. 2009 ; 40( 4-5): 844-847.[citado 2024 set. 06 ] Available from: https://doi.org/10.1016/j.mejo.2008.11.024
  • Fonte: Proceedings. Nome do evento: European Workshop on Low Temperature Electronics. Unidade: EP

    Assunto: MICROELETRÔNICA

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    • ABNT

      PAVANELLO, Marcelo Antonio et al. Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation. 2004, Anais.. Noordwijk: Escola Politécnica, Universidade de São Paulo, 2004. . Acesso em: 06 set. 2024.
    • APA

      Pavanello, M. A., Martino, J. A., Simoen, E., & Claeys, C. (2004). Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation. In Proceedings. Noordwijk: Escola Politécnica, Universidade de São Paulo.
    • NLM

      Pavanello MA, Martino JA, Simoen E, Claeys C. Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation. Proceedings. 2004 ;[citado 2024 set. 06 ]
    • Vancouver

      Pavanello MA, Martino JA, Simoen E, Claeys C. Comparison between drain induced barrier lowering in partially and fully depleted 0.13'mu'm SOI nMOSFETs in low temperature operation. Proceedings. 2004 ;[citado 2024 set. 06 ]
  • Fonte: Microelectronic Engineering. Unidade: EP

    Assunto: MICROELETRÔNICA

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    • ABNT

      PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, v. 36, n. 1-4, p. 375-378, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0167-9317(97)00083-x. Acesso em: 06 set. 2024.
    • APA

      Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, 36( 1-4), 375-378. doi:10.1016/s0167-9317(97)00083-x
    • NLM

      Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2024 set. 06 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x
    • Vancouver

      Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2024 set. 06 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x

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