ReP USP - Resultado da busca

Artigo de periodico
Fast resource and timing aware design optimisation for high-level synthesis (2021)
Perina, André Bannwart ; Silitonga, Arthur ; Becker, Jürgen ; Bonato, Vanderlei
Source: IEEE Transactions on Computers. Unidade: ICMC
Subjects: HARDWARE, ANÁLISE DE DESEMPENHO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, André Bannwart et al. Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, v. 70, n. 12, p. 2070-2082, 2021Tradução . . Disponível em: https://doi.org/10.1109/TC.2021.3112260. Acesso em: 24 dez. 2024.
APA
Perina, A. B., Silitonga, A., Becker, J., & Bonato, V. (2021). Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, 70( 12), 2070-2082. doi:10.1109/TC.2021.3112260
NLM
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 dez. 24 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Vancouver
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 dez. 24 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Trabalho de evento-resumo
Lina: timing-constrained high-level synthesis performance estimator for fast DSE (2019)
Perina, André Bannwart ; Becker, Jürgen ; Bonato, Vanderlei
Source: Proceedings. Conference titles: International Conference on Field-Programmable Technology - ICFPT. Unidade: ICMC
Subjects: CIRCUITOS FPGA, BENCHMARKS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. Lina: timing-constrained high-level synthesis performance estimator for fast DSE. 2019, Anais.. Los Alamitos: IEEE, 2019. Disponível em: https://doi.org/10.1109/ICFPT47387.2019.00063. Acesso em: 24 dez. 2024.
APA
Perina, A. B., Becker, J., & Bonato, V. (2019). Lina: timing-constrained high-level synthesis performance estimator for fast DSE. In Proceedings. Los Alamitos: IEEE. doi:10.1109/ICFPT47387.2019.00063
NLM
Perina AB, Becker J, Bonato V. Lina: timing-constrained high-level synthesis performance estimator for fast DSE [Internet]. Proceedings. 2019 ;[citado 2024 dez. 24 ] Available from: https://doi.org/10.1109/ICFPT47387.2019.00063
Vancouver
Perina AB, Becker J, Bonato V. Lina: timing-constrained high-level synthesis performance estimator for fast DSE [Internet]. Proceedings. 2019 ;[citado 2024 dez. 24 ] Available from: https://doi.org/10.1109/ICFPT47387.2019.00063
Trabalho de evento-resumo
ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis (2019)
Perina, André Bannwart ; Becker, Jürgen ; Bonato, Vanderlei
Source: Proceedings. Conference titles: IEEE International Conference on Electronics, Circuits and Systems - ICECS. Unidade: ICMC
Subjects: COMPUTAÇÃO RECONFIGURÁVEL, HARDWARE, MICROPROGRAMAÇÃO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis. 2019, Anais.. Los Alamitos: IEEE, 2019. Disponível em: https://doi.org/10.1109/ICECS46596.2019.8964669. Acesso em: 24 dez. 2024.
APA
Perina, A. B., Becker, J., & Bonato, V. (2019). ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis. In Proceedings. Los Alamitos: IEEE. doi:10.1109/ICECS46596.2019.8964669
NLM
Perina AB, Becker J, Bonato V. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis [Internet]. Proceedings. 2019 ;[citado 2024 dez. 24 ] Available from: https://doi.org/10.1109/ICECS46596.2019.8964669
Vancouver
Perina AB, Becker J, Bonato V. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis [Internet]. Proceedings. 2019 ;[citado 2024 dez. 24 ] Available from: https://doi.org/10.1109/ICECS46596.2019.8964669

USP Schools

ReP

Filtros

Subjects