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Filtros : "Journal of Signal Processing Systems" Removido: "Indexado no Inspec" Limpar

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  • Artigo de periodico

    Memory aware design optimisation for high-level synthesis (2024)

    Perina, André Bannwart ; Becker, Jürgen ; Bonato, Vanderlei

    Source: Journal of Signal Processing Systems. Unidade: ICMC

    Subjects: COMPUTAÇÃO RECONFIGURÁVEL, CIRCUITOS FPGA, ARQUITETURA DE SOFTWARE

    Disponível em 2026-01-01Acesso à fonteDOIHow to cite
    A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas

    • ABNT

      PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. Memory aware design optimisation for high-level synthesis. Journal of Signal Processing Systems, v. No 2024, n. 11, p. 651-671, 2024Tradução . . Disponível em: https://doi.org/10.1007/s11265-024-01938-3. Acesso em: 29 jun. 2025.

    • APA

      Perina, A. B., Becker, J., & Bonato, V. (2024). Memory aware design optimisation for high-level synthesis. Journal of Signal Processing Systems, No 2024( 11), 651-671. doi:10.1007/s11265-024-01938-3

    • NLM

      Perina AB, Becker J, Bonato V. Memory aware design optimisation for high-level synthesis [Internet]. Journal of Signal Processing Systems. 2024 ; No 2024( 11): 651-671.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-024-01938-3

    • Vancouver

      Perina AB, Becker J, Bonato V. Memory aware design optimisation for high-level synthesis [Internet]. Journal of Signal Processing Systems. 2024 ; No 2024( 11): 651-671.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-024-01938-3

  • Artigo de periodico

    A FAST hardware decoder optimized for template features to obtain order book Data in low latency (2023)

    Oliveira, Caio C. S ; Bonato, Vanderlei

    Source: Journal of Signal Processing Systems. Unidades: ICMC, EESC

    Subjects: HARDWARE, ANÁLISE DE DADOS

    Versão PublicadaAcesso à fonteDOIHow to cite
    A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas

    • ABNT

      OLIVEIRA, Caio C. S e BONATO, Vanderlei. A FAST hardware decoder optimized for template features to obtain order book Data in low latency. Journal of Signal Processing Systems, v. 95, p. 559-567, 2023Tradução . . Disponível em: https://doi.org/10.1007/s11265-023-01850-2. Acesso em: 29 jun. 2025.

    • APA

      Oliveira, C. C. S., & Bonato, V. (2023). A FAST hardware decoder optimized for template features to obtain order book Data in low latency. Journal of Signal Processing Systems, 95, 559-567. doi:10.1007/s11265-023-01850-2

    • NLM

      Oliveira CCS, Bonato V. A FAST hardware decoder optimized for template features to obtain order book Data in low latency [Internet]. Journal of Signal Processing Systems. 2023 ; 95 559-567.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-023-01850-2

    • Vancouver

      Oliveira CCS, Bonato V. A FAST hardware decoder optimized for template features to obtain order book Data in low latency [Internet]. Journal of Signal Processing Systems. 2023 ; 95 559-567.[citado 2025 jun. 29 ] Available from: https://doi.org/10.1007/s11265-023-01850-2
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