Memory aware design optimisation for high-level synthesis (2024)
Perina, André Bannwart 
; Becker, Jürgen ; Bonato, Vanderlei
Source: Journal of Signal Processing Systems. Unidade: ICMC
Subjects: COMPUTAÇÃO RECONFIGURÁVEL, CIRCUITOS FPGA, ARQUITETURA DE SOFTWARE
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ABNT
PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. Memory aware design optimisation for high-level synthesis. Journal of Signal Processing Systems, v. No 2024, n. 11, p. 651-671, 2024Tradução . . Disponível em: https://doi.org/10.1007/s11265-024-01938-3. Acesso em: 05 dez. 2025.APA
Perina, A. B., Becker, J., & Bonato, V. (2024). Memory aware design optimisation for high-level synthesis. Journal of Signal Processing Systems, No 2024( 11), 651-671. doi:10.1007/s11265-024-01938-3NLM
Perina AB, Becker J, Bonato V. Memory aware design optimisation for high-level synthesis [Internet]. Journal of Signal Processing Systems. 2024 ; No 2024( 11): 651-671.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1007/s11265-024-01938-3Vancouver
Perina AB, Becker J, Bonato V. Memory aware design optimisation for high-level synthesis [Internet]. Journal of Signal Processing Systems. 2024 ; No 2024( 11): 651-671.[citado 2025 dez. 05 ] Available from: https://doi.org/10.1007/s11265-024-01938-3
