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Artigo de periodico
A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling (2011)
Castro Márquez, Carlos Iván; Tobar, Edgar Leonardo Romero; Strum, Marius; Wang, Jiang Chau
Source: Journal of Electronic Testing. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CASTRO MÁRQUEZ, Carlos Iván et al. A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling. Journal of Electronic Testing, v. 27, n. 4, p. 485-503, 2011Tradução . . Disponível em: https://doi.org/10.1007/s10836-011-5225-8. Acesso em: 13 nov. 2024.
APA
Castro Márquez, C. I., Tobar, E. L. R., Strum, M., & Wang, J. C. (2011). A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling. Journal of Electronic Testing, 27( 4), 485-503. doi:10.1007/s10836-011-5225-8
NLM
Castro Márquez CI, Tobar ELR, Strum M, Wang JC. A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling [Internet]. Journal of Electronic Testing. 2011 ; 27( 4): 485-503.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1007/s10836-011-5225-8
Vancouver
Castro Márquez CI, Tobar ELR, Strum M, Wang JC. A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling [Internet]. Journal of Electronic Testing. 2011 ; 27( 4): 485-503.[citado 2024 nov. 13 ] Available from: https://doi.org/10.1007/s10836-011-5225-8
Trabalho de evento
The LRD traffic impact on the NoC-based SoCs (2010)
Sepúlveda, Johanna; Strum, Marius; Wang, Jiang Chau ; Pires, Ricardo
Source: Proceedings of the SBCCI'10. Conference titles: Symposium on integrated circuits and systems design. Unidade: EP
Assunto: SEGURANÇA DE REDES
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ABNT
SEPÚLVEDA, Johanna et al. The LRD traffic impact on the NoC-based SoCs. 2010, Anais.. São Paulo: Escola Politécnica, Universidade de São Paulo, 2010. Disponível em: https://doi.org/10.1145/1854153.1854179. Acesso em: 13 nov. 2024.
APA
Sepúlveda, J., Strum, M., Wang, J. C., & Pires, R. (2010). The LRD traffic impact on the NoC-based SoCs. In Proceedings of the SBCCI'10. São Paulo: Escola Politécnica, Universidade de São Paulo. doi:10.1145/1854153.1854179
NLM
Sepúlveda J, Strum M, Wang JC, Pires R. The LRD traffic impact on the NoC-based SoCs [Internet]. Proceedings of the SBCCI'10. 2010 ;[citado 2024 nov. 13 ] Available from: https://doi.org/10.1145/1854153.1854179
Vancouver
Sepúlveda J, Strum M, Wang JC, Pires R. The LRD traffic impact on the NoC-based SoCs [Internet]. Proceedings of the SBCCI'10. 2010 ;[citado 2024 nov. 13 ] Available from: https://doi.org/10.1145/1854153.1854179
Trabalho de evento
A PD-based methodology to enhance efficiency in testbenches with random stimulation (2009)
Castro Márquez, Carlos Iván; Strum, Marius; Wang, Jiang Chau
Source: SBCCI 2009: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: ALGORITMOS
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ABNT
CASTRO MÁRQUEZ, Carlos Iván e STRUM, Marius e WANG, Jiang Chau. A PD-based methodology to enhance efficiency in testbenches with random stimulation. 2009, Anais.. Natal: Sociedade Brasileira de Computação, 2009. Disponível em: https://doi.org/10.1145/1601896.1601921. Acesso em: 13 nov. 2024.
APA
Castro Márquez, C. I., Strum, M., & Wang, J. C. (2009). A PD-based methodology to enhance efficiency in testbenches with random stimulation. In SBCCI 2009: Proceedings. Natal: Sociedade Brasileira de Computação. doi:10.1145/1601896.1601921
NLM
Castro Márquez CI, Strum M, Wang JC. A PD-based methodology to enhance efficiency in testbenches with random stimulation [Internet]. SBCCI 2009: Proceedings. 2009 ;[citado 2024 nov. 13 ] Available from: https://doi.org/10.1145/1601896.1601921
Vancouver
Castro Márquez CI, Strum M, Wang JC. A PD-based methodology to enhance efficiency in testbenches with random stimulation [Internet]. SBCCI 2009: Proceedings. 2009 ;[citado 2024 nov. 13 ] Available from: https://doi.org/10.1145/1601896.1601921
Trabalho de evento
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers (2005)
Oliveira, Duarte Lopes de; Strum, Marius; Wang, Jiang Chau
Source: SBCCI 2005. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Subjects: CONTROLADORES PROGRAMÁVEIS, SISTEMAS DE CONTROLE
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ABNT
OLIVEIRA, Duarte Lopes de e STRUM, Marius e WANG, Jiang Chau. Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. 2005, Anais.. New York: ACM, 2005. . Acesso em: 13 nov. 2024.
APA
Oliveira, D. L. de, Strum, M., & Wang, J. C. (2005). Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. In SBCCI 2005. New York: ACM.
NLM
Oliveira DL de, Strum M, Wang JC. Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI 2005. 2005 ;[citado 2024 nov. 13 ]
Vancouver
Oliveira DL de, Strum M, Wang JC. Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI 2005. 2005 ;[citado 2024 nov. 13 ]
Trabalho de evento
Synthesis of speed-independent circuits from multi-burst graph specification and using gate-level architectures (2001)
Oliveira, Duarte Lopes de; Strum, Marius; Wang, Jiang Chau ; Cunha, Wagner Chiepa
Source: IBERCHIP: proceedings. Conference titles: Workshop IBERCHIP. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS VLSI
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OLIVEIRA, Duarte Lopes de et al. Synthesis of speed-independent circuits from multi-burst graph specification and using gate-level architectures. 2001, Anais.. São Paulo: ABINEE, 2001. . Acesso em: 13 nov. 2024.
APA
Oliveira, D. L. de, Strum, M., Wang, J. C., & Cunha, W. C. (2001). Synthesis of speed-independent circuits from multi-burst graph specification and using gate-level architectures. In IBERCHIP: proceedings. São Paulo: ABINEE.
NLM
Oliveira DL de, Strum M, Wang JC, Cunha WC. Synthesis of speed-independent circuits from multi-burst graph specification and using gate-level architectures. IBERCHIP: proceedings. 2001 ;[citado 2024 nov. 13 ]
Vancouver
Oliveira DL de, Strum M, Wang JC, Cunha WC. Synthesis of speed-independent circuits from multi-burst graph specification and using gate-level architectures. IBERCHIP: proceedings. 2001 ;[citado 2024 nov. 13 ]
Parte de monografia/livro
Behavioral synthesis a user perspective (2001)
Strum, Marius
Source: Design of hardware/software embedded systems. Unidade: EP
Assunto: MONTADORES E COMPILADORES
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ABNT
STRUM, Marius. Behavioral synthesis a user perspective. Design of hardware/software embedded systems. Tradução . Santander: Universidad de Cantabria, 2001. . . Acesso em: 13 nov. 2024.
APA
Strum, M. (2001). Behavioral synthesis a user perspective. In Design of hardware/software embedded systems. Santander: Universidad de Cantabria.
NLM
Strum M. Behavioral synthesis a user perspective. In: Design of hardware/software embedded systems. Santander: Universidad de Cantabria; 2001. [citado 2024 nov. 13 ]
Vancouver
Strum M. Behavioral synthesis a user perspective. In: Design of hardware/software embedded systems. Santander: Universidad de Cantabria; 2001. [citado 2024 nov. 13 ]
Trabalho de evento
Synthesis of multi-burst controllers as standard RS architectures (2001)
Oliveira, Duarte Lopes de; Strum, Marius; Wang, Jiang Chau ; Cunha, Wagner C.
Source: SBMicro 2001: proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: CONTROLE (TEORIA DE SISTEMAS E CONTROLE)
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ABNT
OLIVEIRA, Duarte Lopes de et al. Synthesis of multi-burst controllers as standard RS architectures. 2001, Anais.. Brasília: SBMicro, 2001. . Acesso em: 13 nov. 2024.
APA
Oliveira, D. L. de, Strum, M., Wang, J. C., & Cunha, W. C. (2001). Synthesis of multi-burst controllers as standard RS architectures. In SBMicro 2001: proceedings. Brasília: SBMicro.
NLM
Oliveira DL de, Strum M, Wang JC, Cunha WC. Synthesis of multi-burst controllers as standard RS architectures. SBMicro 2001: proceedings. 2001 ;[citado 2024 nov. 13 ]
Vancouver
Oliveira DL de, Strum M, Wang JC, Cunha WC. Synthesis of multi-burst controllers as standard RS architectures. SBMicro 2001: proceedings. 2001 ;[citado 2024 nov. 13 ]
Trabalho de evento
Direct synthesis of speed-independent circuits using multi-burst graph specification (2000)
Oliveira, Duarte Lopes de; Strum, Marius; Wang, Jiang Chau ; Cunha, Wagner C.
Source: SBMicro 2000: proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OLIVEIRA, Duarte Lopes de et al. Direct synthesis of speed-independent circuits using multi-burst graph specification. 2000, Anais.. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP, 2000. . Acesso em: 13 nov. 2024.
APA
Oliveira, D. L. de, Strum, M., Wang, J. C., & Cunha, W. C. (2000). Direct synthesis of speed-independent circuits using multi-burst graph specification. In SBMicro 2000: proceedings. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP.
NLM
Oliveira DL de, Strum M, Wang JC, Cunha WC. Direct synthesis of speed-independent circuits using multi-burst graph specification. SBMicro 2000: proceedings. 2000 ;[citado 2024 nov. 13 ]
Vancouver
Oliveira DL de, Strum M, Wang JC, Cunha WC. Direct synthesis of speed-independent circuits using multi-burst graph specification. SBMicro 2000: proceedings. 2000 ;[citado 2024 nov. 13 ]
Trabalho de evento
Synthesis of the high performance extended burst mode asynchronous state machines (2000)
Oliveira, Duarte Lopes de; Strum, Marius; Wang, Jiang Chau ; Cunha, Wagner Chiepa
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OLIVEIRA, Duarte Lopes de et al. Synthesis of the high performance extended burst mode asynchronous state machines. 2000, Anais.. Los Alamitos: IEEE, 2000. . Acesso em: 13 nov. 2024.
APA
Oliveira, D. L. de, Strum, M., Wang, J. C., & Cunha, W. C. (2000). Synthesis of the high performance extended burst mode asynchronous state machines. In Proceedings. Los Alamitos: IEEE.
NLM
Oliveira DL de, Strum M, Wang JC, Cunha WC. Synthesis of the high performance extended burst mode asynchronous state machines. Proceedings. 2000 ;[citado 2024 nov. 13 ]
Vancouver
Oliveira DL de, Strum M, Wang JC, Cunha WC. Synthesis of the high performance extended burst mode asynchronous state machines. Proceedings. 2000 ;[citado 2024 nov. 13 ]
Trabalho de evento
On the choice of models of computation for writing executable specifications of system level designs (2000)
Jeukens, Ivan; Strum, Marius
Source: Proceedings. Conference titles: Symposium on Integrated Circuits and Systems Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
JEUKENS, Ivan e STRUM, Marius. On the choice of models of computation for writing executable specifications of system level designs. 2000, Anais.. Los Alamitos: IEEE, 2000. . Acesso em: 13 nov. 2024.
APA
Jeukens, I., & Strum, M. (2000). On the choice of models of computation for writing executable specifications of system level designs. In Proceedings. Los Alamitos: IEEE.
NLM
Jeukens I, Strum M. On the choice of models of computation for writing executable specifications of system level designs. Proceedings. 2000 ;[citado 2024 nov. 13 ]
Vancouver
Jeukens I, Strum M. On the choice of models of computation for writing executable specifications of system level designs. Proceedings. 2000 ;[citado 2024 nov. 13 ]
Trabalho de evento
A study on fast low-power VLSI architectures for turbo codes (2000)
Giulietti, Alexandre; Strum, Marius; Gyselinckx, Bert; van der Perre, Lisbet; Maessen, Francien
Source: SBMicro 2000 : proceedings. Conference titles: International Conference on Microelectronics and Packaging. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GIULIETTI, Alexandre et al. A study on fast low-power VLSI architectures for turbo codes. 2000, Anais.. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP, 2000. . Acesso em: 13 nov. 2024.
APA
Giulietti, A., Strum, M., Gyselinckx, B., van der Perre, L., & Maessen, F. (2000). A study on fast low-power VLSI architectures for turbo codes. In SBMicro 2000 : proceedings. Manaus: SBMicro/UA/UFRGS/UNICAMP/USP.
NLM
Giulietti A, Strum M, Gyselinckx B, van der Perre L, Maessen F. A study on fast low-power VLSI architectures for turbo codes. SBMicro 2000 : proceedings. 2000 ;[citado 2024 nov. 13 ]
Vancouver
Giulietti A, Strum M, Gyselinckx B, van der Perre L, Maessen F. A study on fast low-power VLSI architectures for turbo codes. SBMicro 2000 : proceedings. 2000 ;[citado 2024 nov. 13 ]
Monografia/livro
Sistemas digitales: elementos para un diseño a alto nivel (1999)
Rozo, A G; Wang, Jiang Chau ; Costés, L A; Guerrero, M; López, A; Ploger, P G; Strum, Marius; Vale Neto, José Vieira do; Villar, E; Wilberg, J
Unidade: EP
Assunto: PROCESSAMENTO DIGITAL DE SINAIS
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ABNT
ROZO, A G et al. Sistemas digitales: elementos para un diseño a alto nivel. . Santafé de Bogotá: Uniandes. . Acesso em: 13 nov. 2024. , 1999
APA
Rozo, A. G., Wang, J. C., Costés, L. A., Guerrero, M., López, A., Ploger, P. G., et al. (1999). Sistemas digitales: elementos para un diseño a alto nivel. Santafé de Bogotá: Uniandes.
NLM
Rozo AG, Wang JC, Costés LA, Guerrero M, López A, Ploger PG, Strum M, Vale Neto JV do, Villar E, Wilberg J. Sistemas digitales: elementos para un diseño a alto nivel. 1999 ;[citado 2024 nov. 13 ]
Vancouver
Rozo AG, Wang JC, Costés LA, Guerrero M, López A, Ploger PG, Strum M, Vale Neto JV do, Villar E, Wilberg J. Sistemas digitales: elementos para un diseño a alto nivel. 1999 ;[citado 2024 nov. 13 ]
Relatorio tecnico
A 250 KB/s, K=7, 3-bit soft decision programmable code rate customized Viterbi decoder (1999)
Giulietti, A.; Strum, Marius
Unidade: EP
Assunto: ENGENHARIA ELÉTRICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GIULIETTI, A. e STRUM, Marius. A 250 KB/s, K=7, 3-bit soft decision programmable code rate customized Viterbi decoder. . São Paulo: EPUSP. . Acesso em: 13 nov. 2024. , 1999
APA
Giulietti, A., & Strum, M. (1999). A 250 KB/s, K=7, 3-bit soft decision programmable code rate customized Viterbi decoder. São Paulo: EPUSP.
NLM
Giulietti A, Strum M. A 250 KB/s, K=7, 3-bit soft decision programmable code rate customized Viterbi decoder. 1999 ;[citado 2024 nov. 13 ]
Vancouver
Giulietti A, Strum M. A 250 KB/s, K=7, 3-bit soft decision programmable code rate customized Viterbi decoder. 1999 ;[citado 2024 nov. 13 ]
Relatorio tecnico
An ATM switch model in a hardware-software co-design environment (1999)
Russo Júnior, A.; Nakamura, E. T.; Strum, Marius; Amazonas, José Roberto de Almeida
Unidade: EP
Assunto: REDES DE COMPUTADORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
RUSSO JÚNIOR, A. et al. An ATM switch model in a hardware-software co-design environment. . São Paulo: EPUSP. . Acesso em: 13 nov. 2024. , 1999
APA
Russo Júnior, A., Nakamura, E. T., Strum, M., & Amazonas, J. R. de A. (1999). An ATM switch model in a hardware-software co-design environment. São Paulo: EPUSP.
NLM
Russo Júnior A, Nakamura ET, Strum M, Amazonas JR de A. An ATM switch model in a hardware-software co-design environment. 1999 ;[citado 2024 nov. 13 ]
Vancouver
Russo Júnior A, Nakamura ET, Strum M, Amazonas JR de A. An ATM switch model in a hardware-software co-design environment. 1999 ;[citado 2024 nov. 13 ]
Trabalho de evento
A system level model of an ATM switch using Ptolemy (1997)
Russo Junior, A; Nakamura, E T; Strum, Marius; Amazonas, José Roberto de Almeida
Source: X SBCCI: proceedings. Conference titles: Brazilian Symposium on Integrated Circuit Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
RUSSO JUNIOR, A et al. A system level model of an ATM switch using Ptolemy. 1997, Anais.. Porto Alegre: CPGCC/UFRGS, 1997. . Acesso em: 13 nov. 2024.
APA
Russo Junior, A., Nakamura, E. T., Strum, M., & Amazonas, J. R. de A. (1997). A system level model of an ATM switch using Ptolemy. In X SBCCI: proceedings. Porto Alegre: CPGCC/UFRGS.
NLM
Russo Junior A, Nakamura ET, Strum M, Amazonas JR de A. A system level model of an ATM switch using Ptolemy. X SBCCI: proceedings. 1997 ;[citado 2024 nov. 13 ]
Vancouver
Russo Junior A, Nakamura ET, Strum M, Amazonas JR de A. A system level model of an ATM switch using Ptolemy. X SBCCI: proceedings. 1997 ;[citado 2024 nov. 13 ]
Trabalho de evento
Transformations for functional modules in hierarchical high level synthesis (1997)
Teruya, M Y; Wang, Jiang Chau ; Vale Neto, José Vieira do; Strum, Marius; Jerraya, A A
Source: Proceedings. Conference titles: Brazilian Symposium on Integrated Circuit Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
TERUYA, M Y et al. Transformations for functional modules in hierarchical high level synthesis. 1997, Anais.. Porto Alegre: UFRGS, 1997. . Acesso em: 13 nov. 2024.
APA
Teruya, M. Y., Wang, J. C., Vale Neto, J. V. do, Strum, M., & Jerraya, A. A. (1997). Transformations for functional modules in hierarchical high level synthesis. In Proceedings. Porto Alegre: UFRGS.
NLM
Teruya MY, Wang JC, Vale Neto JV do, Strum M, Jerraya AA. Transformations for functional modules in hierarchical high level synthesis. Proceedings. 1997 ;[citado 2024 nov. 13 ]
Vancouver
Teruya MY, Wang JC, Vale Neto JV do, Strum M, Jerraya AA. Transformations for functional modules in hierarchical high level synthesis. Proceedings. 1997 ;[citado 2024 nov. 13 ]
Trabalho de evento
A strategy for recursive high level synthesis (1997)
Strum, Marius; Vale Neto, José Vieira do; Wang, Jiang Chau ; Teruya, M Y; Jerraya, A A
Source: Proceedings. Conference titles: Brazilian Symposium on Integrated Circuit Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
STRUM, Marius et al. A strategy for recursive high level synthesis. 1997, Anais.. Porto Alegre: UFRGS, 1997. . Acesso em: 13 nov. 2024.
APA
Strum, M., Vale Neto, J. V. do, Wang, J. C., Teruya, M. Y., & Jerraya, A. A. (1997). A strategy for recursive high level synthesis. In Proceedings. Porto Alegre: UFRGS.
NLM
Strum M, Vale Neto JV do, Wang JC, Teruya MY, Jerraya AA. A strategy for recursive high level synthesis. Proceedings. 1997 ;[citado 2024 nov. 13 ]
Vancouver
Strum M, Vale Neto JV do, Wang JC, Teruya MY, Jerraya AA. A strategy for recursive high level synthesis. Proceedings. 1997 ;[citado 2024 nov. 13 ]
Trabalho de evento
Built-in self test high level synthesis. (em CD-Rom) (1997)
Amazonas, José Roberto de Almeida ; Strum, Marius; Vale Neto, José Vieira do; Wang, Jiang Chau ; Rouzeyre, B; Flottes, M L
Source: Proceedings. Conference titles: Conference of the Brazilian Microelectronics Society. Unidade: EP
Subjects: CIRCUITOS INTEGRADOS, SEMICONDUTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
AMAZONAS, José Roberto de Almeida et al. Built-in self test high level synthesis. (em CD-Rom). 1997, Anais.. Itajubá: SBMICRO/EFEI, 1997. . Acesso em: 13 nov. 2024.
APA
Amazonas, J. R. de A., Strum, M., Vale Neto, J. V. do, Wang, J. C., Rouzeyre, B., & Flottes, M. L. (1997). Built-in self test high level synthesis. (em CD-Rom). In Proceedings. Itajubá: SBMICRO/EFEI.
NLM
Amazonas JR de A, Strum M, Vale Neto JV do, Wang JC, Rouzeyre B, Flottes ML. Built-in self test high level synthesis. (em CD-Rom). Proceedings. 1997 ;[citado 2024 nov. 13 ]
Vancouver
Amazonas JR de A, Strum M, Vale Neto JV do, Wang JC, Rouzeyre B, Flottes ML. Built-in self test high level synthesis. (em CD-Rom). Proceedings. 1997 ;[citado 2024 nov. 13 ]
Trabalho de evento
Data path functional unites BIST plan optimization (1997)
Amazonas, José Roberto de Almeida ; Strum, Marius; Vale Neto, José Vieira do; Wang, Jiang Chau ; Rouzeyre, B; Flotters, M L
Conference titles: Brazilian Symposium on Integrated Circuit Design. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
AMAZONAS, José Roberto de Almeida et al. Data path functional unites BIST plan optimization. 1997, Anais.. Porto Alegre: UFRGS, 1997. . Acesso em: 13 nov. 2024.
APA
Amazonas, J. R. de A., Strum, M., Vale Neto, J. V. do, Wang, J. C., Rouzeyre, B., & Flotters, M. L. (1997). Data path functional unites BIST plan optimization. In . Porto Alegre: UFRGS.
NLM
Amazonas JR de A, Strum M, Vale Neto JV do, Wang JC, Rouzeyre B, Flotters ML. Data path functional unites BIST plan optimization. 1997 ;[citado 2024 nov. 13 ]
Vancouver
Amazonas JR de A, Strum M, Vale Neto JV do, Wang JC, Rouzeyre B, Flotters ML. Data path functional unites BIST plan optimization. 1997 ;[citado 2024 nov. 13 ]
Trabalho de evento
A 195KFFT/s (256-points) high performance FFT/IFFT processor for OFDM applications (1996)
Vergara, M; Strum, Marius; Eberle, W; Gyselinckx, B
Source: Proceedings. Conference titles: International Telecommunications Symposium - SBT/IEEE. Unidade: EP
Assunto: ENGENHARIA ELÉTRICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
VERGARA, M et al. A 195KFFT/s (256-points) high performance FFT/IFFT processor for OFDM applications. 1996, Anais.. Piscataway: IEEE, 1996. . Acesso em: 13 nov. 2024.
APA
Vergara, M., Strum, M., Eberle, W., & Gyselinckx, B. (1996). A 195KFFT/s (256-points) high performance FFT/IFFT processor for OFDM applications. In Proceedings. Piscataway: IEEE.
NLM
Vergara M, Strum M, Eberle W, Gyselinckx B. A 195KFFT/s (256-points) high performance FFT/IFFT processor for OFDM applications. Proceedings. 1996 ;[citado 2024 nov. 13 ]
Vancouver
Vergara M, Strum M, Eberle W, Gyselinckx B. A 195KFFT/s (256-points) high performance FFT/IFFT processor for OFDM applications. Proceedings. 1996 ;[citado 2024 nov. 13 ]

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