Built-in self test high level synthesis. (em CD-Rom) (1997)
- Authors:
- USP affiliated authors: AMAZONAS, JOSE ROBERTO DE ALMEIDA - EP ; STRUM, MARIUS - EP ; VALE NETO, JOSE VIEIRA DO - EP ; CHAU, WANG JIANG - EP
- Unidade: EP
- Subjects: CIRCUITOS INTEGRADOS; SEMICONDUTORES
- Language: Inglês
- Imprenta:
- Publisher: SBMICRO/EFEI
- Publisher place: Itajubá
- Date published: 1997
- Source:
- Título: Proceedings
- Conference titles: Conference of the Brazilian Microelectronics Society
-
ABNT
AMAZONAS, José Roberto de Almeida et al. Built-in self test high level synthesis. (em CD-Rom). 1997, Anais.. Itajubá: SBMICRO/EFEI, 1997. . Acesso em: 23 jan. 2026. -
APA
Amazonas, J. R. de A., Strum, M., Vale Neto, J. V. do, Wang, J. C., Rouzeyre, B., & Flottes, M. L. (1997). Built-in self test high level synthesis. (em CD-Rom). In Proceedings. Itajubá: SBMICRO/EFEI. -
NLM
Amazonas JR de A, Strum M, Vale Neto JV do, Wang JC, Rouzeyre B, Flottes ML. Built-in self test high level synthesis. (em CD-Rom). Proceedings. 1997 ;[citado 2026 jan. 23 ] -
Vancouver
Amazonas JR de A, Strum M, Vale Neto JV do, Wang JC, Rouzeyre B, Flottes ML. Built-in self test high level synthesis. (em CD-Rom). Proceedings. 1997 ;[citado 2026 jan. 23 ] - Data path functional units BIST plan optimization: a study-case
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