Source: WSEAS Transactions on Computers. Unidade: ICMC
Subjects: SISTEMAS EMBUTIDOS, COMPUTAÇÃO EVOLUTIVA, ROBÓTICA
ABNT
SILVA, Jorge Luiz e e LOPES, Joelmir José. A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores. WSEAS Transactions on Computers, v. 5, n. 9, p. 429-444, 2010Tradução . . Disponível em: http://www.wseas.us/e-library/transactions/computers/2010/42-418.pdf. Acesso em: 28 ago. 2024.APA
Silva, J. L. e, & Lopes, J. J. (2010). A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores. WSEAS Transactions on Computers, 5( 9), 429-444. Recuperado de http://www.wseas.us/e-library/transactions/computers/2010/42-418.pdfNLM
Silva JL e, Lopes JJ. A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores [Internet]. WSEAS Transactions on Computers. 2010 ; 5( 9): 429-444.[citado 2024 ago. 28 ] Available from: http://www.wseas.us/e-library/transactions/computers/2010/42-418.pdfVancouver
Silva JL e, Lopes JJ. A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores [Internet]. WSEAS Transactions on Computers. 2010 ; 5( 9): 429-444.[citado 2024 ago. 28 ] Available from: http://www.wseas.us/e-library/transactions/computers/2010/42-418.pdf