RTN assessment of traps in polysilicon cylindrical vertical FETs for NVM application (2013)
Caño de Andrade, Maria Glória; Martino, João Antonio 
; Toledano, M; Fourati, Fatima; Degraeve, Robin; Claeys, Cor ; Simoen, Eddy ; Van den Bosch, Geert; Van Houdt, Jan
Fonte: Microelectronic Engineering Volume 109, September 2013, Pages 105-108. Unidade: EP
Assunto: MICROELETRÔNICA
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CAÑO DE ANDRADE, Maria Glória et al. RTN assessment of traps in polysilicon cylindrical vertical FETs for NVM application. Microelectronic Engineering Volume 109, September 2013, Pages 105-108, v. 109, p. 105-108, 2013Tradução . . Disponível em: https://doi.org/10.1016/j.mee.2013.03.019. Acesso em: 20 jun. 2024.APA
Caño de Andrade, M. G., Martino, J. A., Toledano, M., Fourati, F., Degraeve, R., Claeys, C., et al. (2013). RTN assessment of traps in polysilicon cylindrical vertical FETs for NVM application. Microelectronic Engineering Volume 109, September 2013, Pages 105-108, 109, 105-108. doi:10.1016/j.mee.2013.03.019NLM
Caño de Andrade MG, Martino JA, Toledano M, Fourati F, Degraeve R, Claeys C, Simoen E, Van den Bosch G, Van Houdt J. RTN assessment of traps in polysilicon cylindrical vertical FETs for NVM application [Internet]. Microelectronic Engineering Volume 109, September 2013, Pages 105-108. 2013 ; 109 105-108.[citado 2024 jun. 20 ] Available from: https://doi.org/10.1016/j.mee.2013.03.019Vancouver
Caño de Andrade MG, Martino JA, Toledano M, Fourati F, Degraeve R, Claeys C, Simoen E, Van den Bosch G, Van Houdt J. RTN assessment of traps in polysilicon cylindrical vertical FETs for NVM application [Internet]. Microelectronic Engineering Volume 109, September 2013, Pages 105-108. 2013 ; 109 105-108.[citado 2024 jun. 20 ] Available from: https://doi.org/10.1016/j.mee.2013.03.019
