A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA (2018)
Rosa, Leandro de Souza; Dasu, Aravind; Diniz, Pedro C.; Bonato, Vanderlei 
Source: Journal of Signal Processing Systems. Unidade: ICMC
Subjects: COMPUTAÇÃO RECONFIGURÁVEL, SISTEMAS EMBUTIDOS, ROBÓTICA, COMPUTAÇÃO EVOLUTIVA
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ROSA, Leandro de Souza et al. A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA. Journal of Signal Processing Systems, v. 90, n. 3, p. 357-369, 2018Tradução . . Disponível em: https://doi.org/10.1007/s11265-017-1243-9. Acesso em: 27 jul. 2024.APA
Rosa, L. de S., Dasu, A., Diniz, P. C., & Bonato, V. (2018). A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA. Journal of Signal Processing Systems, 90( 3), 357-369. doi:10.1007/s11265-017-1243-9NLM
Rosa L de S, Dasu A, Diniz PC, Bonato V. A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA [Internet]. Journal of Signal Processing Systems. 2018 ; 90( 3): 357-369.[citado 2024 jul. 27 ] Available from: https://doi.org/10.1007/s11265-017-1243-9Vancouver
Rosa L de S, Dasu A, Diniz PC, Bonato V. A Faddeev systolic array for EKF-SLAM and its arithmetic data representation impact on FPGA [Internet]. Journal of Signal Processing Systems. 2018 ; 90( 3): 357-369.[citado 2024 jul. 27 ] Available from: https://doi.org/10.1007/s11265-017-1243-9
