An adjustable size FPGA implementation for an artificial neural network (2001)
Source: Proceedings. Conference titles: International Conference on Artificial Intelligence. Unidade: ICMC
Assunto: REDES NEURAIS
ABNT
WOLF, Denis Fernando e ROMERO, Roseli Aparecida Francelin e MARQUES, Eduardo. An adjustable size FPGA implementation for an artificial neural network. 2001, Anais.. Las Vegas: CSREA, 2001. . Acesso em: 02 jun. 2024.APA
Wolf, D. F., Romero, R. A. F., & Marques, E. (2001). An adjustable size FPGA implementation for an artificial neural network. In Proceedings. Las Vegas: CSREA.NLM
Wolf DF, Romero RAF, Marques E. An adjustable size FPGA implementation for an artificial neural network. Proceedings. 2001 ;[citado 2024 jun. 02 ]Vancouver
Wolf DF, Romero RAF, Marques E. An adjustable size FPGA implementation for an artificial neural network. Proceedings. 2001 ;[citado 2024 jun. 02 ]