Automatic generation of FPGA hardware accelerators using a domain specific language (2009)
Fonte: Proceedings. Nome do evento: International Conference on Field Programmable Logic and Applications - FPL. Unidade: ICMC
Assuntos: ARQUITETURA E ORGANIZAÇÃO DE COMPUTADORES, SISTEMAS EMBUTIDOS, ROBÓTICA, COMPUTAÇÃO EVOLUTIVA
ABNT
MENOTTI, Ricardo et al. Automatic generation of FPGA hardware accelerators using a domain specific language. 2009, Anais.. Los Alamitos, Ca: IEEE Computer Society, 2009. Disponível em: http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485. Acesso em: 09 ago. 2024.APA
Menotti, R., Cardoso, J. M. P., Fernandes, M. M., & Marques, E. (2009). Automatic generation of FPGA hardware accelerators using a domain specific language. In Proceedings. Los Alamitos, Ca: IEEE Computer Society. Recuperado de http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485NLM
Menotti R, Cardoso JMP, Fernandes MM, Marques E. Automatic generation of FPGA hardware accelerators using a domain specific language [Internet]. Proceedings. 2009 ;[citado 2024 ago. 09 ] Available from: http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485Vancouver
Menotti R, Cardoso JMP, Fernandes MM, Marques E. Automatic generation of FPGA hardware accelerators using a domain specific language [Internet]. Proceedings. 2009 ;[citado 2024 ago. 09 ] Available from: http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485