Automatic generation of FPGA hardware accelerators using a domain specific language

Automatic generation of FPGA hardware accelerators using a domain specific language (2009)

Authors:
Autor USP: MARQUES, EDUARDO - ICMC
Unidade: ICMC
Subjects: ARQUITETURA E ORGANIZAÇÃO DE COMPUTADORES; SISTEMAS EMBUTIDOS; ROBÓTICA; COMPUTAÇÃO EVOLUTIVA
Language: Português
Imprenta:
- Publisher: IEEE Computer Society
- Publisher place: Los Alamitos, Ca
- Date published: 2009
Source:
- Título: Proceedings
- ISSN: 1946-1488
Conference titles: International Conference on Field Programmable Logic and Applications - FPL

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ABNT

MENOTTI, Ricardo et al. Automatic generation of FPGA hardware accelerators using a domain specific language. 2009, Anais.. Los Alamitos, Ca: IEEE Computer Society, 2009. Disponível em: http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485. Acesso em: 11 fev. 2026.
APA

Menotti, R., Cardoso, J. M. P., Fernandes, M. M., & Marques, E. (2009). Automatic generation of FPGA hardware accelerators using a domain specific language. In Proceedings. Los Alamitos, Ca: IEEE Computer Society. Recuperado de http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485
NLM

Menotti R, Cardoso JMP, Fernandes MM, Marques E. Automatic generation of FPGA hardware accelerators using a domain specific language [Internet]. Proceedings. 2009 ;[citado 2026 fev. 11 ] Available from: http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485
Vancouver

Menotti R, Cardoso JMP, Fernandes MM, Marques E. Automatic generation of FPGA hardware accelerators using a domain specific language [Internet]. Proceedings. 2009 ;[citado 2026 fev. 11 ] Available from: http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485