Source: Journal of Integrated Circuits and Systems. Unidades: EP, EESC
Subjects: TRANSISTORES, NANOELETRÔNICA, TEMPERATURA
ABNT
SIMOEN, Eddy et al. Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications. Journal of Integrated Circuits and Systems, v. 17, n. 2, p. 1-9, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17i2.617. Acesso em: 13 nov. 2024.APA
Simoen, E., Coelho, C. H. S., Silva, V. C. P. da, Martino, J. A., Agopian, P. G. D., Oliveira, A., et al. (2022). Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications. Journal of Integrated Circuits and Systems, 17( 2), 1-9. doi:10.29292/jics.v17i2.617NLM
Simoen E, Coelho CHS, Silva VCP da, Martino JA, Agopian PGD, Oliveira A, Cretu B, Veloso A. Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-9.[citado 2024 nov. 13 ] Available from: https://doi.org/10.29292/jics.v17i2.617Vancouver
Simoen E, Coelho CHS, Silva VCP da, Martino JA, Agopian PGD, Oliveira A, Cretu B, Veloso A. Performance perspective of gate-all-around double nanosheet CMOS beyond high-speed logic applications [Internet]. Journal of Integrated Circuits and Systems. 2022 ; 17( 2): 1-9.[citado 2024 nov. 13 ] Available from: https://doi.org/10.29292/jics.v17i2.617