Adding tightly-integrated task scheduling acceleration to a RISC-V multi-core processor (2019)
- Authors:
- USP affiliated authors: LEJBMAN, ALFREDO GOLDMAN VEL - IME ; MORAIS, LUCAS HENRIQUE - IME ; SILVA, VITOR BORGES DA - IME
- Unidade: IME
- DOI: 10.1145/3352460.3358271
- Assunto: PROGRAMAÇÃO PARALELA
- Agências de fomento:
- Language: Inglês
- Imprenta:
- Source:
- Título: Proceedings
- Conference titles: Annual IEEE/ACM International Symposium on Microarchitecture - MICRO
- Este periódico é de assinatura
- Este artigo NÃO é de acesso aberto
- Cor do Acesso Aberto: closed
-
ABNT
MORAIS, Lucas Henrique et al. Adding tightly-integrated task scheduling acceleration to a RISC-V multi-core processor. 2019, Anais.. New York: ACM, 2019. Disponível em: https://doi.org/10.1145/3352460.3358271. Acesso em: 01 jan. 2026. -
APA
Morais, L. H., Silva, V. B. da, Goldman, A., Alvarez , C., Bosch, J., Frank, M., & Araujo, G. (2019). Adding tightly-integrated task scheduling acceleration to a RISC-V multi-core processor. In Proceedings. New York: ACM. doi:10.1145/3352460.3358271 -
NLM
Morais LH, Silva VB da, Goldman A, Alvarez C, Bosch J, Frank M, Araujo G. Adding tightly-integrated task scheduling acceleration to a RISC-V multi-core processor [Internet]. Proceedings. 2019 ;[citado 2026 jan. 01 ] Available from: https://doi.org/10.1145/3352460.3358271 -
Vancouver
Morais LH, Silva VB da, Goldman A, Alvarez C, Bosch J, Frank M, Araujo G. Adding tightly-integrated task scheduling acceleration to a RISC-V multi-core processor [Internet]. Proceedings. 2019 ;[citado 2026 jan. 01 ] Available from: https://doi.org/10.1145/3352460.3358271 - Using Petri-Net modelling to support the case for HW-assisted task scheduling
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Informações sobre o DOI: 10.1145/3352460.3358271 (Fonte: oaDOI API)
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