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Artigo de periodico
Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor (2005)
Cerdeira, Antonio ; Alemán, Miguel A.; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis ; Vancaillie, Laurent
Fonte: IEEE Transactions on Electron Devices. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CERDEIRA, Antonio et al. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, v. 52, n. 5, p. 967-972, 2005Tradução . . Disponível em: https://doi.org/10.1109/ted.2005.846327. Acesso em: 16 nov. 2025.
APA
Cerdeira, A., Alemán, M. A., Pavanello, M. A., Martino, J. A., Flandre, D., & Vancaillie, L. (2005). Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, 52( 5), 967-972. doi:10.1109/ted.2005.846327
NLM
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1109/ted.2005.846327
Vancouver
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1109/ted.2005.846327
Trabalho de evento
On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET (2004)
Cerdeira, Antonio ; Alemán, Miguel A; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Vancaillie, Laurent; Flandre, Denis
Fonte: ICCDCS 2004. Nome do evento: IEEE International Caracas Conference on Devices, Circuits and Systems. Unidade: EP
Assuntos: TRANSISTORES, CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CERDEIRA, Antonio et al. On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. 2004, Anais.. New York: IEEE, 2004. . Acesso em: 16 nov. 2025.
APA
Cerdeira, A., Alemán, M. A., Pavanello, M. A., Martino, J. A., Vancaillie, L., & Flandre, D. (2004). On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. In ICCDCS 2004. New York: IEEE.
NLM
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Vancaillie L, Flandre D. On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. ICCDCS 2004. 2004 ;[citado 2025 nov. 16 ]
Vancouver
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Vancaillie L, Flandre D. On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. ICCDCS 2004. 2004 ;[citado 2025 nov. 16 ]
Artigo de periodico
Low temperature operation of graded-channel SOI nMOSFETs for analog applications (2002)
Pavanello, Marcelo Antonio ; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Flandre, Denis
Fonte: Journal de Physique IV. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV, v. 12, n. 3, 2002Tradução . . Disponível em: https://doi.org/10.1051/jp420020030. Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., Agopian, P. G. D., Martino, J. A., & Flandre, D. (2002). Low temperature operation of graded-channel SOI nMOSFETs for analog applications. Journal de Physique IV, 12( 3). doi:10.1051/jp420020030
NLM
Pavanello MA, Agopian PGD, Martino JA, Flandre D. Low temperature operation of graded-channel SOI nMOSFETs for analog applications [Internet]. Journal de Physique IV. 2002 ;12( 3):[citado 2025 nov. 16 ] Available from: https://doi.org/10.1051/jp420020030
Vancouver
Pavanello MA, Agopian PGD, Martino JA, Flandre D. Low temperature operation of graded-channel SOI nMOSFETs for analog applications [Internet]. Journal de Physique IV. 2002 ;12( 3):[citado 2025 nov. 16 ] Available from: https://doi.org/10.1051/jp420020030
Artigo de periodico
Low temperature operation of 0.13 µm partially-depleted SOI nMOSFETs with floating body (2002)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Mercha, A.; Rafi, J.M.; Simoen, Eddy ; Claeys, Cor ; Van Meer, H.; De Meyer, K.
Fonte: Journal de Physique IV. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Low temperature operation of 0.13 µm partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV, v. 12, n. 3, 2002Tradução . . Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., Mercha, A., Rafi, J. M., Simoen, E., Claeys, C., et al. (2002). Low temperature operation of 0.13 µm partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV, 12( 3).
NLM
Pavanello MA, Martino JA, Mercha A, Rafi JM, Simoen E, Claeys C, Van Meer H, De Meyer K. Low temperature operation of 0.13 µm partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV. 2002 ;12( 3):[citado 2025 nov. 16 ]
Vancouver
Pavanello MA, Martino JA, Mercha A, Rafi JM, Simoen E, Claeys C, Van Meer H, De Meyer K. Low temperature operation of 0.13 µm partially-depleted SOI nMOSFETs with floating body. Journal de Physique IV. 2002 ;12( 3):[citado 2025 nov. 16 ]
Artigo de periodico
An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics (2000)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Dessard, Vincent; Flandre, Denis
Fonte: Electrochemical and Solid-State Letters. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochemical and Solid-State Letters, v. 3, n. Ja 2000, p. 50-52, 2000Tradução . . Disponível em: https://doi.org/10.1149/1.1390955. Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., Dessard, V., & Flandre, D. (2000). An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics. Electrochemical and Solid-State Letters, 3( Ja 2000), 50-52. doi:10.1149/1.1390955
NLM
Pavanello MA, Martino JA, Dessard V, Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics [Internet]. Electrochemical and Solid-State Letters. 2000 ; 3( Ja 2000): 50-52.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1149/1.1390955
Vancouver
Pavanello MA, Martino JA, Dessard V, Flandre D. An asymmetric channel SOI nMOSFET for reducing parasitic effects and improving output characteristics [Internet]. Electrochemical and Solid-State Letters. 2000 ; 3( Ja 2000): 50-52.[citado 2025 nov. 16 ] Available from: https://doi.org/10.1149/1.1390955
Artigo de periodico
Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's (1999)
Pavanello, Marcelo Antonio ; Martino, João Antonio
Fonte: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics, 1999Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(99)00178-1. Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., & Martino, J. A. (1999). Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's. Solid-State Electronics. doi:10.1016/s0038-1101(99)00178-1
NLM
Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1
Vancouver
Pavanello MA, Martino JA. Extraction of the oxide charges at the silicon substrate interface in silicon-on-insulator MOSFET's [Internet]. Solid-State Electronics. 1999 ;[citado 2025 nov. 16 ] Available from: https://doi.org/10.1016/s0038-1101(99)00178-1
Artigo de periodico
Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures (1996)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Fonte: Journal de Physique IV Colloque 3, supplement au Journal de Physique III. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III, v. 6, 1996Tradução . . Acesso em: 16 nov. 2025.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1996). Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III, 6.
NLM
Pavanello MA, Martino JA, Colinge J-P. Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III. 1996 ;6[citado 2025 nov. 16 ]
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III. 1996 ;6[citado 2025 nov. 16 ]

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