Silva, V C P; Martino, João Antonio 
; Simoen, Eddy ; Veloso, Anabela; Agopian, Paula Ghedini Der
Fonte: Solid State Electronics. Unidade: EP
Assuntos: TRANSISTORES, TEMPERATURA, NANOTECNOLOGIA, CIRCUITOS ANALÓGICOS, CIRCUITOS DIGITAIS
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SILVA, V C P et al. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, v. 208, p. 1-5, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108729. Acesso em: 08 nov. 2024.APA
Silva, V. C. P., Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2023). Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, 208, 1-5. doi:10.1016/j.sse.2023.108729NLM
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2024 nov. 08 ] Available from: https://doi.org/10.1016/j.sse.2023.108729Vancouver
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2024 nov. 08 ] Available from: https://doi.org/10.1016/j.sse.2023.108729
