ReP USP - Resultado da busca

Trabalho de evento
Liquid helium temperature operation of graded-channel SOI nMOSFETs (2012)
Souza, Michelly de ; Kilchytska, Valeriya ; Flandre, Denis ; Pavanello, Marcelo Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SOUZA, Michelly de et al. Liquid helium temperature operation of graded-channel SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0135ecst. Acesso em: 01 out. 2024.
APA
Souza, M. de, Kilchytska, V., Flandre, D., & Pavanello, M. A. (2012). Liquid helium temperature operation of graded-channel SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0135ecst
NLM
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0135ecst
Vancouver
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0135ecst
Trabalho de evento
Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements (2012)
Mariniello, Genaro ; Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MARINIELLO, Genaro et al. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0231ecst. Acesso em: 01 out. 2024.
APA
Mariniello, G., Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0231ecst
NLM
Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0231ecst
Vancouver
Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0231ecst
Trabalho de evento
On the variability of the low-frequency noise in UTBOX SOI nMOSFETs (2012)
Simoen, Eddy ; Caño de Andrade, Maria Glória ; Almeida, Luciano Mendes; Aoulaiche, Marc; Caillat, Christian; Jurczak, Malgorzata; Claeys, Cor
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SIMOEN, Eddy et al. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0051ecst. Acesso em: 01 out. 2024.
APA
Simoen, E., Caño de Andrade, M. G., Almeida, L. M., Aoulaiche, M., Caillat, C., Jurczak, M., & Claeys, C. (2012). On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0051ecst
NLM
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0051ecst
Vancouver
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0051ecst
Trabalho de evento
Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors (2012)
Trevisoli, Renan ; Doria, Rodrigo Trevisoli ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
TREVISOLI, Renan et al. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0207ecst. Acesso em: 01 out. 2024.
APA
Trevisoli, R., Doria, R. T., Souza, M. de, & Pavanello, M. A. (2012). Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0207ecst
NLM
Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0207ecst
Vancouver
Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0207ecst
Trabalho de evento
Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance (2012)
Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
DORIA, Rodrigo Trevisoli et al. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0215ecst. Acesso em: 01 out. 2024.
APA
Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0215ecst
NLM
Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0215ecst
Vancouver
Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0215ecst
Trabalho de evento
Simulation of a Miller OpAmp with FinFETs at High temperatures (2012)
Contreras, Esteban ; Cerdeira, Antonio ; Pavanello, Marcelo Antonio
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CONTRERAS, Esteban e CERDEIRA, Antonio e PAVANELLO, Marcelo Antonio. Simulation of a Miller OpAmp with FinFETs at High temperatures. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0177ecst. Acesso em: 01 out. 2024.
APA
Contreras, E., Cerdeira, A., & Pavanello, M. A. (2012). Simulation of a Miller OpAmp with FinFETs at High temperatures. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0177ecst
NLM
Contreras E, Cerdeira A, Pavanello MA. Simulation of a Miller OpAmp with FinFETs at High temperatures [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0177ecst
Vancouver
Contreras E, Cerdeira A, Pavanello MA. Simulation of a Miller OpAmp with FinFETs at High temperatures [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0177ecst
Trabalho de evento
MEMS-based ultrasound transducer: CMUT modeling and fabrication process (2012)
Oliveira, Victor Inacio de; Ibrahim, Ricardo Cury ; Barros, Ettore Apolônio de ; Mendonça, Lucas Gonçalves Dias; Lima, Bruno Luis Soares de ; Piazzeta, Maria Helena de Oliveira; Gobbi, Angelo Luiz
Fonte: Microelectronics technology and devices, SBMicro. Nome do evento: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
OLIVEIRA, Victor Inacio de et al. MEMS-based ultrasound transducer: CMUT modeling and fabrication process. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0431ecst. Acesso em: 01 out. 2024.
APA
Oliveira, V. I. de, Ibrahim, R. C., Barros, E. A. de, Mendonça, L. G. D., Lima, B. L. S. de, Piazzeta, M. H. de O., & Gobbi, A. L. (2012). MEMS-based ultrasound transducer: CMUT modeling and fabrication process. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0431ecst
NLM
Oliveira VI de, Ibrahim RC, Barros EA de, Mendonça LGD, Lima BLS de, Piazzeta MH de O, Gobbi AL. MEMS-based ultrasound transducer: CMUT modeling and fabrication process [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0431ecst
Vancouver
Oliveira VI de, Ibrahim RC, Barros EA de, Mendonça LGD, Lima BLS de, Piazzeta MH de O, Gobbi AL. MEMS-based ultrasound transducer: CMUT modeling and fabrication process [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 out. 01 ] Available from: https://doi.org/10.1149/04901.0431ecst

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