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  • Source: Semiconductor Science and Technology. Unidade: EP

    Assunto: SEMICONDUTORES

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    • ABNT

      MARTINO, Márcio Dalla Valle; CLAEYS, Cor; AGOPIAN, Paula Ghedini Der; et al. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology[S.l.], v. 33, n. 7, p. 075012, 2018. Disponível em: < https://doi.org/10.1088/1361-6641/aac4fd > DOI: 10.1088/1361-6641/aac4fd.
    • APA

      Martino, M. D. V., Claeys, C., Agopian, P. G. D., Rooyackers, R., Simoen, E., & Martino, J. A. (2018). Performance of differential pair circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, 33( 7), 075012. doi:10.1088/1361-6641/aac4fd
    • NLM

      Martino MDV, Claeys C, Agopian PGD, Rooyackers R, Simoen E, Martino JA. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2018 ; 33( 7): 075012.Available from: https://doi.org/10.1088/1361-6641/aac4fd
    • Vancouver

      Martino MDV, Claeys C, Agopian PGD, Rooyackers R, Simoen E, Martino JA. Performance of differential pair circuits designed with line tunnel FET devices at different temperatures [Internet]. Semiconductor Science and Technology. 2018 ; 33( 7): 075012.Available from: https://doi.org/10.1088/1361-6641/aac4fd
  • Source: Semiconductor Science and Technology. Unidades: EP, EACH

    Subjects: TEMPERATURA, SEMICONDUTORES

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    • ABNT

      CAPARROZ, Luís Felipe Vicentis; AGOPIAN, Paula Ghedini Der; CLAEYS, Cor; et al. Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K. Semiconductor Science and Technology[S.l.], v. 33, n. 6, p. 065003, 2018. Disponível em: < https://doi.org/10.1088/1361-6641/aabab3 > DOI: 10.1088/1361-6641/aabab3.
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      Caparroz, L. F. V., Agopian, P. G. D., Claeys, C., Simoen, E., Bordallo, C. C. M., & Martino, J. A. (2018). Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K. Semiconductor Science and Technology, 33( 6), 065003. doi:10.1088/1361-6641/aabab3
    • NLM

      Caparroz LFV, Agopian PGD, Claeys C, Simoen E, Bordallo CCM, Martino JA. Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K [Internet]. Semiconductor Science and Technology. 2018 ; 33( 6): 065003.Available from: https://doi.org/10.1088/1361-6641/aabab3
    • Vancouver

      Caparroz LFV, Agopian PGD, Claeys C, Simoen E, Bordallo CCM, Martino JA. Analysis of proton irradiated n- and p-type strained FinFETs at low temperatures down to 100 K [Internet]. Semiconductor Science and Technology. 2018 ; 33( 6): 065003.Available from: https://doi.org/10.1088/1361-6641/aabab3
  • Source: Composants nanoélectroniques. Unidade: EP

    Assunto: SEMICONDUTORES

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      BORDALLO, Caio Cesar Mendes; MOCUTA, Dan; COLLAERT, Nadine; et al. The impact of the temperature on In0.53Ga0.47As nTFETs. Composants nanoélectroniques[S.l.], v. 18, n. 1, 2018. Disponível em: < https://doi.org/10.21494/iste.op.2018.0224 > DOI: 10.21494/iste.op.2018.0224.
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      Bordallo, C. C. M., Mocuta, D., Collaert, N., Alian, A., Simoen, E., Claeys, C., et al. (2018). The impact of the temperature on In0.53Ga0.47As nTFETs. Composants nanoélectroniques, 18( 1). doi:10.21494/iste.op.2018.0224
    • NLM

      Bordallo CCM, Mocuta D, Collaert N, Alian A, Simoen E, Claeys C, Agopian PGD, Martino JA, Rooyackers R, Mols Y, Van Dooren A, Verhulst AS, Lin D. The impact of the temperature on In0.53Ga0.47As nTFETs [Internet]. Composants nanoélectroniques. 2018 ;18( 1):Available from: https://doi.org/10.21494/iste.op.2018.0224
    • Vancouver

      Bordallo CCM, Mocuta D, Collaert N, Alian A, Simoen E, Claeys C, Agopian PGD, Martino JA, Rooyackers R, Mols Y, Van Dooren A, Verhulst AS, Lin D. The impact of the temperature on In0.53Ga0.47As nTFETs [Internet]. Composants nanoélectroniques. 2018 ;18( 1):Available from: https://doi.org/10.21494/iste.op.2018.0224
  • Source: Journal of Integrated Circuits and Systems. Unidade: EP

    Assunto: SEMICONDUTORES

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    • ABNT

      ITOCAZU, Vitor Tatsuo; SONNENBERG, Victor; MARTINO, João Antonio; SIMOEN, Eddy; CLAEYS, Cor. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems[S.l.], v. 12, n. 2, p. 82-88, 2017. DOI: 10.29292/jics.v12i2.455.
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      Itocazu, V. T., Sonnenberg, V., Martino, J. A., Simoen, E., & Claeys, C. (2017). Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems, 12( 2), 82-88. doi:10.29292/jics.v12i2.455
    • NLM

      Itocazu VT, Sonnenberg V, Martino JA, Simoen E, Claeys C. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems. 2017 ; 12( 2): 82-88.
    • Vancouver

      Itocazu VT, Sonnenberg V, Martino JA, Simoen E, Claeys C. Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies. Journal of Integrated Circuits and Systems. 2017 ; 12( 2): 82-88.
  • Source: IEEE Transactions on Electron Devices. Unidade: EP

    Subjects: MICROELETRÔNICA, SEMICONDUTORES

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      BORDALLO, Caio Cesar Mendes; COLLAERT, Nadine; CLAEYS, Cor; et al. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices[S.l.], v. 64, n. 9, p. 3595-3600, 2017. Disponível em: < https://doi.org/10.1109/ted.2017.2721110 > DOI: 10.1109/TED.2017.2721110.
    • APA

      Bordallo, C. C. M., Collaert, N., Claeys, C., Simoen, E., Vandooren, A., Rooyackers, R., et al. (2017). The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs. IEEE Transactions on Electron Devices, 64( 9), 3595-3600. doi:10.1109/TED.2017.2721110
    • NLM

      Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.Available from: https://doi.org/10.1109/ted.2017.2721110
    • Vancouver

      Bordallo CCM, Collaert N, Claeys C, Simoen E, Vandooren A, Rooyackers R, Mols Y, Alian A, Agopian PGD, Martino JA. The Influence of Oxide Thickness and Indium Amount on the Analog Parameters of InxGa1–xAs nTFETs [Internet]. IEEE Transactions on Electron Devices. 2017 ; 64( 9): 3595-3600.Available from: https://doi.org/10.1109/ted.2017.2721110
  • Source: Semiconductor Science and Technology. Unidade: EP

    Subjects: TRANSISTORES, SEMICONDUTORES

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    • ABNT

      MARTINO, Márcio Dalla Valle; CLAEYS, Cor; ROOYACKERS, Rita; et al. Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology[S.l.], v. 32, n. 5, p. 055015, 2017. DOI: 10.1088/1361-6641/aa6764.
    • APA

      Martino, M. D. V., Claeys, C., Rooyackers, R., Simoen, E., Agopian, P. G. D., Vandooren, A., & Martino, J. A. (2017). Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology, 32( 5), 055015. doi:10.1088/1361-6641/aa6764
    • NLM

      Martino MDV, Claeys C, Rooyackers R, Simoen E, Agopian PGD, Vandooren A, Martino JA. Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology. 2017 ; 32( 5): 055015.
    • Vancouver

      Martino MDV, Claeys C, Rooyackers R, Simoen E, Agopian PGD, Vandooren A, Martino JA. Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures. Semiconductor Science and Technology. 2017 ; 32( 5): 055015.
  • Source: Solid-State Electronics Volume 128, February 2017, Pages 43-47. Unidade: EP

    Assunto: SEMICONDUTORES

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      AGOPIAN, Paula Ghedini Der; COLLAERT, Nadine; ALIAN, A; et al. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures. Solid-State Electronics Volume 128, February 2017, Pages 43-47[S.l.], v. 128, p. 43-47, 2017. Disponível em: < https://doi.org/10.1016/j.sse.2016.10.021 > DOI: 10.1016/j.sse.2016.10.021.
    • APA

      Agopian, P. G. D., Collaert, N., Alian, A., Simoen, E., Claeys, C., & Martino, J. A. (2017). Study of line-TFET analog performance comparing with other TFET and MOSFET architectures. Solid-State Electronics Volume 128, February 2017, Pages 43-47, 128, 43-47. doi:10.1016/j.sse.2016.10.021
    • NLM

      Agopian PGD, Collaert N, Alian A, Simoen E, Claeys C, Martino JA. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures [Internet]. Solid-State Electronics Volume 128, February 2017, Pages 43-47. 2017 ; 128 43-47.Available from: https://doi.org/10.1016/j.sse.2016.10.021
    • Vancouver

      Agopian PGD, Collaert N, Alian A, Simoen E, Claeys C, Martino JA. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures [Internet]. Solid-State Electronics Volume 128, February 2017, Pages 43-47. 2017 ; 128 43-47.Available from: https://doi.org/10.1016/j.sse.2016.10.021
  • Source: Semiconductor Science and Technology. Unidade: EP

    Subjects: SEMICONDUTORES, MICROELETRÔNICA

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      OLIVEIRA, Alberto Vinicius de; AGOPIAN, Paula Ghedini Der; SIMOEN, Eddy; et al. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology[S.l.], v. 31, n. 11, p. 114002 , 2016. Disponível em: < https://doi.org/10.1088/0268-1242/31/11/114002 > DOI: 10.1088/0268-1242/31/11/114002.
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      Oliveira, A. V. de, Agopian, P. G. D., Simoen, E., Langer, R., Collaert, N., Thean, A., et al. (2016). Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes. Semiconductor Science and Technology, 31( 11), 114002 . doi:10.1088/0268-1242/31/11/114002
    • NLM

      Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .Available from: https://doi.org/10.1088/0268-1242/31/11/114002
    • Vancouver

      Oliveira AV de, Agopian PGD, Simoen E, Langer R, Collaert N, Thean A, Claeys C, Martino JA. Split CV mobility at low temperature operation of Ge pFinFETs fabricated with STI first and last processes [Internet]. Semiconductor Science and Technology. 2016 ; 31( 11): 114002 .Available from: https://doi.org/10.1088/0268-1242/31/11/114002
  • Source: Journal of Integrated Circuits and Systems. Unidade: EP

    Assunto: SEMICONDUTORES

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      ITOCAZU, Vitor Tatsuo; SONNENBERG, Victor; MARTINO, João Antonio; et al. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems[S.l.], v. 12, n. 2, p. 101-106, 2016. DOI: 10.29292/jics.v12i2.458.
    • APA

      Itocazu, V. T., Sonnenberg, V., Martino, J. A., Sasaki, K. R. A., Simoen, E., & Claeys, C. (2016). Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems, 12( 2), 101-106. doi:10.29292/jics.v12i2.458
    • NLM

      Itocazu VT, Sonnenberg V, Martino JA, Sasaki KRA, Simoen E, Claeys C. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems. 2016 ; 12( 2): 101-106.
    • Vancouver

      Itocazu VT, Sonnenberg V, Martino JA, Sasaki KRA, Simoen E, Claeys C. Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation. Journal of Integrated Circuits and Systems. 2016 ; 12( 2): 101-106.
  • Source: Semiconductor Science and Technology. Unidade: EP

    Assunto: SEMICONDUTORES

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      MARTINO, Márcio Dalla Valle; MARTINO, João Antonio; AGOPIAN, Paula Ghedini Der; et al. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures. Semiconductor Science and Technology[S.l.], v. 31, n. 5, 2016. Disponível em: < https://doi.org/10.1088/0268-1242/31/5/055001 > DOI: 10.1088/0268-1242/31/5/055001.
    • APA

      Martino, M. D. V., Martino, J. A., Agopian, P. G. D., Vandooren, A., Rooyackers, R., Simoen, E., & Claeys, C. (2016). Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures. Semiconductor Science and Technology, 31( 5). doi:10.1088/0268-1242/31/5/055001
    • NLM

      Martino MDV, Martino JA, Agopian PGD, Vandooren A, Rooyackers R, Simoen E, Claeys C. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures [Internet]. Semiconductor Science and Technology. 2016 ; 31( 5):Available from: https://doi.org/10.1088/0268-1242/31/5/055001
    • Vancouver

      Martino MDV, Martino JA, Agopian PGD, Vandooren A, Rooyackers R, Simoen E, Claeys C. Performance of TFET and FinFET devices applied to current mirrors for different dimensions and temperatures [Internet]. Semiconductor Science and Technology. 2016 ; 31( 5):Available from: https://doi.org/10.1088/0268-1242/31/5/055001
  • Source: IEEE Transactions on Electron Devices. Unidade: EP

    Subjects: TRANSISTORES, SILÍCIO

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      BORDALLO, Caio Cesar Mendes; CLAEYS, Cor; THEAN, Aaron; et al. Impact of the NW-TFET Diameter on the Efficiency and the Intrinsic Voltage Gain From a Conduction Regime Perspective. IEEE Transactions on Electron Devices[S.l.], v. 63, n. 7, p. 2930-2935, 2016. Disponível em: < https://doi.org/10.1109/ted.2016.2559580 > DOI: 10.1109/ted.2016.2559580.
    • APA

      Bordallo, C. C. M., Claeys, C., Thean, A., Simoen, E., Vandooren, A., Agopian, P. G. D., et al. (2016). Impact of the NW-TFET Diameter on the Efficiency and the Intrinsic Voltage Gain From a Conduction Regime Perspective. IEEE Transactions on Electron Devices, 63( 7), 2930-2935. doi:10.1109/ted.2016.2559580
    • NLM

      Bordallo CCM, Claeys C, Thean A, Simoen E, Vandooren A, Agopian PGD, Sivieri V de B, Martino JA, Rooyackers R. Impact of the NW-TFET Diameter on the Efficiency and the Intrinsic Voltage Gain From a Conduction Regime Perspective [Internet]. IEEE Transactions on Electron Devices. 2016 ; 63( 7): 2930-2935.Available from: https://doi.org/10.1109/ted.2016.2559580
    • Vancouver

      Bordallo CCM, Claeys C, Thean A, Simoen E, Vandooren A, Agopian PGD, Sivieri V de B, Martino JA, Rooyackers R. Impact of the NW-TFET Diameter on the Efficiency and the Intrinsic Voltage Gain From a Conduction Regime Perspective [Internet]. IEEE Transactions on Electron Devices. 2016 ; 63( 7): 2930-2935.Available from: https://doi.org/10.1109/ted.2016.2559580
  • Source: ECS Transactions volume 66 issue 5 on pages 309 to 314. Unidade: EP

    Subjects: MICROELETRÔNICA, TRANSISTORES

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      OLIVEIRA, Alberto Vinicius de; SIMOEN, Eddy; THEAN, Aaron; et al. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs. ECS Transactions volume 66 issue 5 on pages 309 to 314[S.l.], v. 66, n. 5, p. 309-314, 2016. Disponível em: < https://doi.org/10.1149/06605.0309ecst > DOI: 10.29292/jics.v11i1.424.
    • APA

      Oliveira, A. V. de, Simoen, E., Thean, A., Agopian, P. G. D., Martino, J. A., Claeys, C., et al. (2016). Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs. ECS Transactions volume 66 issue 5 on pages 309 to 314, 66( 5), 309-314. doi:10.29292/jics.v11i1.424
    • NLM

      Oliveira AV de, Simoen E, Thean A, Agopian PGD, Martino JA, Claeys C, Mertens H, Collaert N. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs [Internet]. ECS Transactions volume 66 issue 5 on pages 309 to 314. 2016 ; 66( 5): 309-314.Available from: https://doi.org/10.1149/06605.0309ecst
    • Vancouver

      Oliveira AV de, Simoen E, Thean A, Agopian PGD, Martino JA, Claeys C, Mertens H, Collaert N. Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs [Internet]. ECS Transactions volume 66 issue 5 on pages 309 to 314. 2016 ; 66( 5): 309-314.Available from: https://doi.org/10.1149/06605.0309ecst
  • Source: Solid-State Electronics. Unidade: EP

    Subjects: SEMICONDUTORES, MICROELETRÔNICA

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      OLIVEIRA, Alberto Vinicius de; COLLAERT, Nadine; THEAN, Aaron; et al. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics[S.l.], v. 123, p. 124-129, 2016. Disponível em: < https://doi.org/10.1016/j.sse.2016.05.004 > DOI: 10.1016/j.sse.2016.05.004.
    • APA

      Oliveira, A. V. de, Collaert, N., Thean, A., Claeys, C., Simoen, E., Agopian, P. G. D., & Martino, J. A. (2016). Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures. Solid-State Electronics, 123, 124-129. doi:10.1016/j.sse.2016.05.004
    • NLM

      Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.Available from: https://doi.org/10.1016/j.sse.2016.05.004
    • Vancouver

      Oliveira AV de, Collaert N, Thean A, Claeys C, Simoen E, Agopian PGD, Martino JA. Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures [Internet]. Solid-State Electronics. 2016 ; 123 124-129.Available from: https://doi.org/10.1016/j.sse.2016.05.004
  • Source: Solid-State Electronics. Unidade: EP

    Subjects: SEMICONDUTORES, MICROELETRÔNICA

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      SASAKI, Kátia Regina Akemi; MANINI, Matheus Barros; CLAEYS, Cor; SIMOEN, Eddy; MARTINO, João Antonio. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs. Solid-State Electronics[S.l.], v. 112, p. 19-23, 2015. Disponível em: < https://doi.org/10.1016/j.sse.2015.02.011 > DOI: 10.1016/j.sse.2015.02.011.
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      Sasaki, K. R. A., Manini, M. B., Claeys, C., Simoen, E., & Martino, J. A. (2015). Enhanced dynamic threshold voltage UTBB SOI nMOSFETs. Solid-State Electronics, 112, 19-23. doi:10.1016/j.sse.2015.02.011
    • NLM

      Sasaki KRA, Manini MB, Claeys C, Simoen E, Martino JA. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs [Internet]. Solid-State Electronics. 2015 ; 112 19-23.Available from: https://doi.org/10.1016/j.sse.2015.02.011
    • Vancouver

      Sasaki KRA, Manini MB, Claeys C, Simoen E, Martino JA. Enhanced dynamic threshold voltage UTBB SOI nMOSFETs [Internet]. Solid-State Electronics. 2015 ; 112 19-23.Available from: https://doi.org/10.1016/j.sse.2015.02.011
  • Source: J. Low Power Electron. Appl. 2015, 5(2), 69-80. Unidade: EP

    Assunto: MICROELETRÔNICA

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      SASAKI, Kátia Regina Akemi; AOULAICHE, Marc; SIMOEN, Eddy; CLAEYS, Cor; MARTINO, João Antonio. Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View. J. Low Power Electron. Appl. 2015, 5(2), 69-80[S.l.], v. 5, n. 2, p. 69-80, 2015. Disponível em: < https://doi.org/10.3390/jlpea5020069 > DOI: 10.3390/jlpea5020069.
    • APA

      Sasaki, K. R. A., Aoulaiche, M., Simoen, E., Claeys, C., & Martino, J. A. (2015). Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View. J. Low Power Electron. Appl. 2015, 5(2), 69-80, 5( 2), 69-80. doi:10.3390/jlpea5020069
    • NLM

      Sasaki KRA, Aoulaiche M, Simoen E, Claeys C, Martino JA. Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View [Internet]. J. Low Power Electron. Appl. 2015, 5(2), 69-80. 2015 ; 5( 2): 69-80.Available from: https://doi.org/10.3390/jlpea5020069
    • Vancouver

      Sasaki KRA, Aoulaiche M, Simoen E, Claeys C, Martino JA. Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View [Internet]. J. Low Power Electron. Appl. 2015, 5(2), 69-80. 2015 ; 5( 2): 69-80.Available from: https://doi.org/10.3390/jlpea5020069
  • Source: Microelectronic Engineering. Unidade: EP

    Assunto: MICROELETRÔNICA

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      DORIA, Rodrigo Trevisoli; CLAEYS, Cor; SIMOEN, Eddy; SOUZA, Marcio Alves Sodré de; MARTINO, João Antonio. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs. Microelectronic Engineering[S.l.], v. 147, n. 1, p. 92-95, 2015. Disponível em: < https://doi.org/10.1016/j.mee.2015.04.056 > DOI: 10.1016/j.mee.2015.04.056.
    • APA

      Doria, R. T., Claeys, C., Simoen, E., Souza, M. A. S. de, & Martino, J. A. (2015). In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs. Microelectronic Engineering, 147( 1), 92-95. doi:10.1016/j.mee.2015.04.056
    • NLM

      Doria RT, Claeys C, Simoen E, Souza MAS de, Martino JA. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs [Internet]. Microelectronic Engineering. 2015 ; 147( 1): 92-95.Available from: https://doi.org/10.1016/j.mee.2015.04.056
    • Vancouver

      Doria RT, Claeys C, Simoen E, Souza MAS de, Martino JA. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs [Internet]. Microelectronic Engineering. 2015 ; 147( 1): 92-95.Available from: https://doi.org/10.1016/j.mee.2015.04.056
  • Source: Solid-State Electronics. Unidade: EP

    Assunto: MICROELETRÔNICA

    Acesso à fonteDOIHow to cite
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    • ABNT

      BÜHLER, Rudolf Theoderich; AGOPIAN, Paula Ghedini Der; COLLAERT, Nadine; et al. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics[S.l.], v. 103, p. 209-215, 2015. Disponível em: < https://doi.org/10.1016/j.sse.2014.07.010 > DOI: 10.1016/j.sse.2014.07.010.
    • APA

      Bühler, R. T., Agopian, P. G. D., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2015). Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs. Solid-State Electronics, 103, 209-215. doi:10.1016/j.sse.2014.07.010
    • NLM

      Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.Available from: https://doi.org/10.1016/j.sse.2014.07.010
    • Vancouver

      Bühler RT, Agopian PGD, Collaert N, Simoen E, Claeys C, Martino JA. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs [Internet]. Solid-State Electronics. 2015 ;103 209-215.Available from: https://doi.org/10.1016/j.sse.2014.07.010
  • Source: Solid-State Electronics. Unidade: EP

    Subjects: TRANSISTORES, MICROELETRÔNICA

    Acesso à fonteDOIHow to cite
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    • ABNT

      MARTINO, Márcio Dalla Valle; THEAN, Aaron; CLAEYS, Cor; et al. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism. Solid-State Electronics[S.l.], v. 112, p. 51-55, 2015. Disponível em: < https://doi.org/10.1016/j.sse.2015.02.006 > DOI: 10.1016/j.sse.2015.02.006.
    • APA

      Martino, M. D. V., Thean, A., Claeys, C., Neves, F. S., Agopian, P. G. D., Martino, J. A., et al. (2015). Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism. Solid-State Electronics, 112, 51-55. doi:10.1016/j.sse.2015.02.006
    • NLM

      Martino MDV, Thean A, Claeys C, Neves FS, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism [Internet]. Solid-State Electronics. 2015 ; 112 51-55.Available from: https://doi.org/10.1016/j.sse.2015.02.006
    • Vancouver

      Martino MDV, Thean A, Claeys C, Neves FS, Agopian PGD, Martino JA, Vandooren A, Rooyackers R, Simoen E. Analog performance of vertical nanowire TFETs as a function of temperature and transport mechanism [Internet]. Solid-State Electronics. 2015 ; 112 51-55.Available from: https://doi.org/10.1016/j.sse.2015.02.006
  • Source: Microelectronics Reliability. Unidade: EP

    Subjects: SILÍCIO, MICROELETRÔNICA

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    • ABNT

      CAÑO DE ANDRADE, Maria Glória; COLLAERT, Nadine; SIMOEN, Eddy; et al. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation. Microelectronics Reliability[S.l.], v. 54, n. 11, p. 2349-2354, 2014. Disponível em: < https://doi.org/10.1016/j.microrel.2014.06.013 > DOI: 10.1016/j.microrel.2014.06.013.
    • APA

      Caño de Andrade, M. G., Collaert, N., Simoen, E., Claeys, C., Aoulaiche, M., & Martino, J. A. (2014). Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation. Microelectronics Reliability, 54( 11), 2349-2354. doi:10.1016/j.microrel.2014.06.013
    • NLM

      Caño de Andrade MG, Collaert N, Simoen E, Claeys C, Aoulaiche M, Martino JA. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation [Internet]. Microelectronics Reliability. 2014 ; 54( 11): 2349-2354.Available from: https://doi.org/10.1016/j.microrel.2014.06.013
    • Vancouver

      Caño de Andrade MG, Collaert N, Simoen E, Claeys C, Aoulaiche M, Martino JA. Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation [Internet]. Microelectronics Reliability. 2014 ; 54( 11): 2349-2354.Available from: https://doi.org/10.1016/j.microrel.2014.06.013
  • Source: Solid-State Electronics. Unidade: EP

    Assunto: MICROELETRÔNICA

    Acesso à fonteDOIHow to cite
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    • ABNT

      ORTIZ-CONDE, Adelmo; MARTINO, João Antonio; GARCIA- SANCHEZ, Francisco J.; et al. Threshold voltage extraction in Tunnel FETs. Solid-State Electronics[S.l.], v. 93, p. 49-55, 2014. Disponível em: < https://doi.org/10.1016/j.sse.2013.12.010 > DOI: 10.1016/j.sse.2013.12.010.
    • APA

      Ortiz-Conde, A., Martino, J. A., Garcia- Sanchez, F. J., Muci, J., Martino, J. A., Agopian, P. G. D., & Claeys, C. (2014). Threshold voltage extraction in Tunnel FETs. Solid-State Electronics, 93, 49-55. doi:10.1016/j.sse.2013.12.010
    • NLM

      Ortiz-Conde A, Martino JA, Garcia- Sanchez FJ, Muci J, Martino JA, Agopian PGD, Claeys C. Threshold voltage extraction in Tunnel FETs [Internet]. Solid-State Electronics. 2014 ; 93 49-55.Available from: https://doi.org/10.1016/j.sse.2013.12.010
    • Vancouver

      Ortiz-Conde A, Martino JA, Garcia- Sanchez FJ, Muci J, Martino JA, Agopian PGD, Claeys C. Threshold voltage extraction in Tunnel FETs [Internet]. Solid-State Electronics. 2014 ; 93 49-55.Available from: https://doi.org/10.1016/j.sse.2013.12.010

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