Fast resource and timing aware design optimisation for high-level synthesis (2021)
Perina, André Bannwart 
; Silitonga, Arthur ; Becker, Jürgen ; Bonato, Vanderlei
Fonte: IEEE Transactions on Computers. Unidade: ICMC
Assuntos: HARDWARE, ANÁLISE DE DESEMPENHO
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ABNT
PERINA, André Bannwart et al. Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, v. 70, n. 12, p. 2070-2082, 2021Tradução . . Disponível em: https://doi.org/10.1109/TC.2021.3112260. Acesso em: 30 set. 2024.APA
Perina, A. B., Silitonga, A., Becker, J., & Bonato, V. (2021). Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, 70( 12), 2070-2082. doi:10.1109/TC.2021.3112260NLM
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 set. 30 ] Available from: https://doi.org/10.1109/TC.2021.3112260Vancouver
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 set. 30 ] Available from: https://doi.org/10.1109/TC.2021.3112260
