A partition model using partial reconfigurable hardware for chipCflow project (2012)
- Autores:
- Autor USP: SILVA, JORGE LUIZ E - ICMC
- Unidade: ICMC
- Assuntos: SISTEMAS EMBUTIDOS; COMPUTAÇÃO EVOLUTIVA; ROBÓTICA
- Idioma: Inglês
- Imprenta:
- Fonte:
- Título do periódico: Proceedings
- Nome do evento: Jornadas SARTECO - JS2012
-
ABNT
SOUZA JUNIOR, Francisco e SILVA, Jorge Luiz e. A partition model using partial reconfigurable hardware for chipCflow project. 2012, Anais.. Madrid: SARTECO, 2012. . Acesso em: 19 abr. 2024. -
APA
Souza Junior, F., & Silva, J. L. e. (2012). A partition model using partial reconfigurable hardware for chipCflow project. In Proceedings. Madrid: SARTECO. -
NLM
Souza Junior F, Silva JL e. A partition model using partial reconfigurable hardware for chipCflow project. Proceedings. 2012 ;[citado 2024 abr. 19 ] -
Vancouver
Souza Junior F, Silva JL e. A partition model using partial reconfigurable hardware for chipCflow project. Proceedings. 2012 ;[citado 2024 abr. 19 ] - A benchmark approach for compilers in reconfigurable hardware
- Research and partial analysis of overhead of a partition model for a partially reconfigurable hardware in a data-driven machine-chicflow
- Tag management in a reconfigurable tagged-token dataflow architecture
- A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores
- Execution of algorithms using a dynamic dataflow model for reconfigurable hardware: a purpose for matching data
- RtrASSoc51 - adaptable superscalar reconfigurable programmable system on chip: the reconfigurable tools for DSR a development system
- C commands Implemented direct into the hardware using the ChipCflow Machine
- RtrASSoc51-rI2C (reconfigurable inter integrated circuit)
- The ChipCflow: a tool to generate hardware accelerators using a static dataflow machine designed for a FPGA
- Execution of algorithms using a dynamic dataflow model for reconfigurable hardware: commands in dataflow graph
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