A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores (2010)
- Autores:
- Autor USP: SILVA, JORGE LUIZ E - ICMC
- Unidade: ICMC
- Assuntos: SISTEMAS EMBUTIDOS; COMPUTAÇÃO EVOLUTIVA; ROBÓTICA
- Idioma: Inglês
- Imprenta:
- Fonte:
- Título do periódico: WSEAS Transactions on Computers
- ISSN: 1109-2750
- Volume/Número/Paginação/Ano: v. 5, n. 9, p. 429-444, 2010
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ABNT
SILVA, Jorge Luiz e e LOPES, Joelmir José. A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores. WSEAS Transactions on Computers, v. 5, n. 9, p. 429-444, 2010Tradução . . Disponível em: http://www.wseas.us/e-library/transactions/computers/2010/42-418.pdf. Acesso em: 23 abr. 2024. -
APA
Silva, J. L. e, & Lopes, J. J. (2010). A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores. WSEAS Transactions on Computers, 5( 9), 429-444. Recuperado de http://www.wseas.us/e-library/transactions/computers/2010/42-418.pdf -
NLM
Silva JL e, Lopes JJ. A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores [Internet]. WSEAS Transactions on Computers. 2010 ; 5( 9): 429-444.[citado 2024 abr. 23 ] Available from: http://www.wseas.us/e-library/transactions/computers/2010/42-418.pdf -
Vancouver
Silva JL e, Lopes JJ. A dynamic dataflow architecture using partial reconfigurable hardware as an option for multiple cores [Internet]. WSEAS Transactions on Computers. 2010 ; 5( 9): 429-444.[citado 2024 abr. 23 ] Available from: http://www.wseas.us/e-library/transactions/computers/2010/42-418.pdf - A benchmark approach for compilers in reconfigurable hardware
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