Impact of the graded-channel architecture on double gate transistors for high-performance analog applications (2003)
- Authors:
- USP affiliated authors: MARTINO, JOÃO ANTONIO - EP ; PAVANELLO, MARCELO ANTONIO - EP
- Unidade: EP
- Assunto: MICROELETRÔNICA
- Language: Inglês
- Imprenta:
- Publisher: The Electrochemical Society
- Publisher place: Pennington
- Date published: 2003
- Source:
- Título do periódico: Silicon-on-Insulator Technology and Devices XI: proceedings
- Conference titles: International Symposium on SOI Technology and Devices
-
ABNT
PAVANELLO, Marcelo Antonio et al. Impact of the graded-channel architecture on double gate transistors for high-performance analog applications. Silicon-on-Insulator Technology and Devices XI: proceedings. Tradução . Pennington: The Electrochemical Society, 2003. . . Acesso em: 17 abr. 2024. -
APA
Pavanello, M. A., Martino, J. A., Chung, T. M., Kranti, A., Raskin, J. -P., & Flandre, D. (2003). Impact of the graded-channel architecture on double gate transistors for high-performance analog applications. In Silicon-on-Insulator Technology and Devices XI: proceedings. Pennington: The Electrochemical Society. -
NLM
Pavanello MA, Martino JA, Chung TM, Kranti A, Raskin J-P, Flandre D. Impact of the graded-channel architecture on double gate transistors for high-performance analog applications. In: Silicon-on-Insulator Technology and Devices XI: proceedings. Pennington: The Electrochemical Society; 2003. [citado 2024 abr. 17 ] -
Vancouver
Pavanello MA, Martino JA, Chung TM, Kranti A, Raskin J-P, Flandre D. Impact of the graded-channel architecture on double gate transistors for high-performance analog applications. In: Silicon-on-Insulator Technology and Devices XI: proceedings. Pennington: The Electrochemical Society; 2003. [citado 2024 abr. 17 ] - Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range
- Behavior of graded channel SOI gate-all-around NMOSFET devices at high temperatures
- Comparison between conventional and graded-channel SOI nMOSFETs in low temperature operation
- Analog performance of graded-channel SOI NMOSFETS at low temperatures
- Analysis of deep submicrometer bulk and fully depleted soi nmosfet analog operation at cryogenic temperatures
- Physical characterization and reliability aspects of MuGFETs
- A study on the self-heating effect in deep-submicrometer partially depleted SOI MOSFETs at low temperatures
- Halo effect on 0.13 'mu'm floating-body partially depleted SOI n-Mosfets in low temperature operation
- Analog circuit design using graded-channel silicon-on-insulator nMOSFETs
- Performance of source follower buffers implemented with standard and strained triple-gate nFinFETs
How to cite
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
