Back gate voltage influence on the LDD SOI NMOSFET series resistence extraction from 150 to 300 k (1998)
- Authors:
- Autor USP: MARTINO, JOÃO ANTONIO - EP
- Unidade: EP
- Assunto: SEMICONDUTORES
- Language: Inglês
- Imprenta:
- Publisher: National Academy of Sciences of Ukraine
- Publisher place: Kyiv
- Date published: 1998
- Source:
- Título do periódico: Perspectives, science and technologies for novel silicon on insulator devices
- Conference titles: Nato Advanced Research Workshop
-
ABNT
NICOLETT, Aparecido Sirley et al. Back gate voltage influence on the LDD SOI NMOSFET series resistence extraction from 150 to 300 k. 1998, Anais.. Kyiv: National Academy of Sciences of Ukraine, 1998. . Acesso em: 19 abr. 2024. -
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (1998). Back gate voltage influence on the LDD SOI NMOSFET series resistence extraction from 150 to 300 k. In Perspectives, science and technologies for novel silicon on insulator devices. Kyiv: National Academy of Sciences of Ukraine. -
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Back gate voltage influence on the LDD SOI NMOSFET series resistence extraction from 150 to 300 k. Perspectives, science and technologies for novel silicon on insulator devices. 1998 ;[citado 2024 abr. 19 ] -
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Back gate voltage influence on the LDD SOI NMOSFET series resistence extraction from 150 to 300 k. Perspectives, science and technologies for novel silicon on insulator devices. 1998 ;[citado 2024 abr. 19 ] - Temperature influences on the drain leakage current behavior in graded-channel SOI nMOSFETs
- Projeto de processos de fabricação avançados aplicáveis nas tecnologias CMOS micrométricas
- Analysis of the linear kink effect in partially depleted SOI nMOSFETs
- Simple method to extract the length dependent mobility degradation factor at 77 K
- Mobility degradation influence on the SOI MOSFET channel length extraction at 77K
- Low temperature and channel engineering influence on harmonic distortion of soi nmosfets for analog applications
- Analysis of the capacitance vs. voltage in graded channel SOI capacitor
- A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction
- Metodo simples para a obtencao da densidade de armadilhas na primeira e segunda interface em soi-mosfet
- Simple method for the determination of the interface trap density at 77k in fully depleted acumulation mode soi mosfets
How to cite
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
