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Filtros : "International Conference on Field Programmable Logic and Applications - FPL" Limpar

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Trabalho de evento-resumo
Design space exploration based on multiobjective genetic algorithms and clustering-based high-level estimation (2013)
Martins, Luiz Gustavo Almeida ; Marques, Eduardo
Source: Proceedings. Conference titles: International Conference on Field Programmable Logic and Applications - FPL. Unidade: ICMC
Subjects: ARQUITETURA E ORGANIZAÇÃO DE COMPUTADORES, ALGORITMOS GENÉTICOS, APRENDIZADO COMPUTACIONAL
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MARTINS, Luiz Gustavo Almeida e MARQUES, Eduardo. Design space exploration based on multiobjective genetic algorithms and clustering-based high-level estimation. 2013, Anais.. Piscataway: IEEE, 2013. Disponível em: https://doi.org/10.1109/FPL.2013.6645608. Acesso em: 04 dez. 2025.
APA
Martins, L. G. A., & Marques, E. (2013). Design space exploration based on multiobjective genetic algorithms and clustering-based high-level estimation. In Proceedings. Piscataway: IEEE. doi:10.1109/FPL.2013.6645608
NLM
Martins LGA, Marques E. Design space exploration based on multiobjective genetic algorithms and clustering-based high-level estimation [Internet]. Proceedings. 2013 ;[citado 2025 dez. 04 ] Available from: https://doi.org/10.1109/FPL.2013.6645608
Vancouver
Martins LGA, Marques E. Design space exploration based on multiobjective genetic algorithms and clustering-based high-level estimation [Internet]. Proceedings. 2013 ;[citado 2025 dez. 04 ] Available from: https://doi.org/10.1109/FPL.2013.6645608
Trabalho de evento
Automatic generation of FPGA hardware accelerators using a domain specific language (2009)
Menotti, Ricardo; Cardoso, João Manuel Paiva; Fernandes, Marcio Merino; Marques, Eduardo
Source: Proceedings. Conference titles: International Conference on Field Programmable Logic and Applications - FPL. Unidade: ICMC
Subjects: ARQUITETURA E ORGANIZAÇÃO DE COMPUTADORES, SISTEMAS EMBUTIDOS, ROBÓTICA, COMPUTAÇÃO EVOLUTIVA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MENOTTI, Ricardo et al. Automatic generation of FPGA hardware accelerators using a domain specific language. 2009, Anais.. Los Alamitos, Ca: IEEE Computer Society, 2009. Disponível em: http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485. Acesso em: 04 dez. 2025.
APA
Menotti, R., Cardoso, J. M. P., Fernandes, M. M., & Marques, E. (2009). Automatic generation of FPGA hardware accelerators using a domain specific language. In Proceedings. Los Alamitos, Ca: IEEE Computer Society. Recuperado de http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485
NLM
Menotti R, Cardoso JMP, Fernandes MM, Marques E. Automatic generation of FPGA hardware accelerators using a domain specific language [Internet]. Proceedings. 2009 ;[citado 2025 dez. 04 ] Available from: http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485
Vancouver
Menotti R, Cardoso JMP, Fernandes MM, Marques E. Automatic generation of FPGA hardware accelerators using a domain specific language [Internet]. Proceedings. 2009 ;[citado 2025 dez. 04 ] Available from: http://ieeexplore.ieee.org/stamp/stamp.do?tp=&arnumber=5272485

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