A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution (1994)
Gray, C T; Liu, W; Van Noije, Wilhelmus Adrianus Maria 
; Hugues Junior, A; Cavin, R K
Fonte: Ieee Journal of Solid-State Circuits. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
GRAY, C T et al. A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. Ieee Journal of Solid-State Circuits, v. 29, n. 3 , p. 340-9, 1994Tradução . . Acesso em: 04 dez. 2025.APA
Gray, C. T., Liu, W., Van Noije, W. A. M., Hugues Junior, A., & Cavin, R. K. (1994). A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. Ieee Journal of Solid-State Circuits, 29( 3 ), 340-9.NLM
Gray CT, Liu W, Van Noije WAM, Hugues Junior A, Cavin RK. A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. Ieee Journal of Solid-State Circuits. 1994 ;29( 3 ): 340-9.[citado 2025 dez. 04 ]Vancouver
Gray CT, Liu W, Van Noije WAM, Hugues Junior A, Cavin RK. A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. Ieee Journal of Solid-State Circuits. 1994 ;29( 3 ): 340-9.[citado 2025 dez. 04 ]
