ReP USP - Resultado da busca

Artigo de periodico
Analog operation and harmonic distortion temperature dependence of nMOS junctionless transistors (2010)
Doria, Rodrigo Trevisoli ; Pavanello, Marcelo Antonio ; Lee, C. W.; Ferain, Isabelle; Akhavan, Nima Dehdashti; Yan, Ran; Razavi, Pedram; Yu, Ran; Kranti, A; Colinge, Jean-Pierre
Fonte: Microelectronics Technology and Devices - SBMicro 2010. Unidade: EP
Assunto: ELETROQUÍMICA
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ABNT
DORIA, Rodrigo Trevisoli et al. Analog operation and harmonic distortion temperature dependence of nMOS junctionless transistors. Microelectronics Technology and Devices - SBMicro 2010, v. 31, n. 1, p. 13-20, 2010Tradução . . Disponível em: https://doi.org/10.1149/1.3474137. Acesso em: 03 dez. 2025.
APA
Doria, R. T., Pavanello, M. A., Lee, C. W., Ferain, I., Akhavan, N. D., Yan, R., et al. (2010). Analog operation and harmonic distortion temperature dependence of nMOS junctionless transistors. Microelectronics Technology and Devices - SBMicro 2010, 31( 1), 13-20. doi:10.1149/1.3474137
NLM
Doria RT, Pavanello MA, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Kranti A, Colinge J-P. Analog operation and harmonic distortion temperature dependence of nMOS junctionless transistors [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 13-20.[citado 2025 dez. 03 ] Available from: https://doi.org/10.1149/1.3474137
Vancouver
Doria RT, Pavanello MA, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Kranti A, Colinge J-P. Analog operation and harmonic distortion temperature dependence of nMOS junctionless transistors [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 13-20.[citado 2025 dez. 03 ] Available from: https://doi.org/10.1149/1.3474137
Artigo de periodico
Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k (1997)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Fonte: Microelectronic Engineering. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, v. 36, n. 1-4, p. 375-378, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0167-9317(97)00083-x. Acesso em: 03 dez. 2025.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k. Microelectronic Engineering, 36( 1-4), 375-378. doi:10.1016/s0167-9317(97)00083-x
NLM
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2025 dez. 03 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77k [Internet]. Microelectronic Engineering. 1997 ; 36( 1-4): 375-378.[citado 2025 dez. 03 ] Available from: https://doi.org/10.1016/s0167-9317(97)00083-x
Artigo de periodico
Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature (1997)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Fonte: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature. Solid-State Electronics, v. 41, n. 9, p. 1241-1246, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(97)00071-3. Acesso em: 03 dez. 2025.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature. Solid-State Electronics, 41( 9), 1241-1246. doi:10.1016/s0038-1101(97)00071-3
NLM
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature [Internet]. Solid-State Electronics. 1997 ; 41( 9): 1241-1246.[citado 2025 dez. 03 ] Available from: https://doi.org/10.1016/s0038-1101(97)00071-3
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Analytical modeling of the substrate influences on accumulation-mode SOI pMOSFETs at room temperature and at liquid nitrogen temperature [Internet]. Solid-State Electronics. 1997 ; 41( 9): 1241-1246.[citado 2025 dez. 03 ] Available from: https://doi.org/10.1016/s0038-1101(97)00071-3
Artigo de periodico
Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K (1997)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Fonte: Solid-State Electronics. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K. Solid-State Electronics, v. 41, n. ja 1997, p. 111-119, 1997Tradução . . Disponível em: https://doi.org/10.1016/s0038-1101(96)00126-8. Acesso em: 03 dez. 2025.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1997). Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K. Solid-State Electronics, 41( ja 1997), 111-119. doi:10.1016/s0038-1101(96)00126-8
NLM
Pavanello MA, Martino JA, Colinge J-P. Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K [Internet]. Solid-State Electronics. 1997 ; 41( ja 1997): 111-119.[citado 2025 dez. 03 ] Available from: https://doi.org/10.1016/s0038-1101(96)00126-8
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Substrate influences on fully depleted enhacement mode SOI MOSFETs at room temperature and 77 K [Internet]. Solid-State Electronics. 1997 ; 41( ja 1997): 111-119.[citado 2025 dez. 03 ] Available from: https://doi.org/10.1016/s0038-1101(96)00126-8
Artigo de periodico
Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures (1996)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Fonte: Journal de Physique IV Colloque 3, supplement au Journal de Physique III. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III, v. 6, 1996Tradução . . Acesso em: 03 dez. 2025.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1996). Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III, 6.
NLM
Pavanello MA, Martino JA, Colinge J-P. Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III. 1996 ;6[citado 2025 dez. 03 ]
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Theoretical and experimental study of the substrate effect on the fully depleted SOI MOSFET at low temperatures. Journal de Physique IV Colloque 3, supplement au Journal de Physique III. 1996 ;6[citado 2025 dez. 03 ]
Trabalho de evento
Theoretical and experimental analysis of the substrate effect on accumulation mode p-channel soi mosfet at room and at liquid nitrogen temperature (1996)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Colinge, Jean-Pierre
Fonte: Proceedings. Nome do evento: Conference of the Brazilian Microelectronics Society. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio e MARTINO, João Antonio e COLINGE, Jean-Pierre. Theoretical and experimental analysis of the substrate effect on accumulation mode p-channel soi mosfet at room and at liquid nitrogen temperature. 1996, Anais.. São Paulo: Sbmicro, 1996. . Acesso em: 03 dez. 2025.
APA
Pavanello, M. A., Martino, J. A., & Colinge, J. -P. (1996). Theoretical and experimental analysis of the substrate effect on accumulation mode p-channel soi mosfet at room and at liquid nitrogen temperature. In Proceedings. São Paulo: Sbmicro.
NLM
Pavanello MA, Martino JA, Colinge J-P. Theoretical and experimental analysis of the substrate effect on accumulation mode p-channel soi mosfet at room and at liquid nitrogen temperature. Proceedings. 1996 ;[citado 2025 dez. 03 ]
Vancouver
Pavanello MA, Martino JA, Colinge J-P. Theoretical and experimental analysis of the substrate effect on accumulation mode p-channel soi mosfet at room and at liquid nitrogen temperature. Proceedings. 1996 ;[citado 2025 dez. 03 ]
Trabalho de evento
An analytical model for the potential drop in the silicon substrate on thin film SOI Mosfet's and its influence on the threshold voltage (1990)
Martino, João Antonio ; Lauwers, L.; Colinge, Jean-Pierre
Fonte: Anais. Nome do evento: Congresso da Sociedade Brasileira de Microeletrônica. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MARTINO, João Antonio e LAUWERS, L. e COLINGE, Jean-Pierre. An analytical model for the potential drop in the silicon substrate on thin film SOI Mosfet's and its influence on the threshold voltage. 1990, Anais.. Campinas: SBM, 1990. Disponível em: https://doi.org/10.1117/12.26296. Acesso em: 03 dez. 2025.
APA
Martino, J. A., Lauwers, L., & Colinge, J. -P. (1990). An analytical model for the potential drop in the silicon substrate on thin film SOI Mosfet's and its influence on the threshold voltage. In Anais. Campinas: SBM. doi:10.1117/12.26296
NLM
Martino JA, Lauwers L, Colinge J-P. An analytical model for the potential drop in the silicon substrate on thin film SOI Mosfet's and its influence on the threshold voltage [Internet]. Anais. 1990 ;[citado 2025 dez. 03 ] Available from: https://doi.org/10.1117/12.26296
Vancouver
Martino JA, Lauwers L, Colinge J-P. An analytical model for the potential drop in the silicon substrate on thin film SOI Mosfet's and its influence on the threshold voltage [Internet]. Anais. 1990 ;[citado 2025 dez. 03 ] Available from: https://doi.org/10.1117/12.26296

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