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Tese (Doutorado)
Applying Rosenbrock method for solving stiff ODEs raised from the chemical reactivity of the atmosphere through heterogeneous architectures based on FPGAs (2023)
Souza Junior, Carlos Alberto Oliveira de ; Diniz, Pedro Nuno Cruz (coorient); Marques, Eduardo (Orientador)
Unidade: ICMC
Subjects: HARDWARE, CIRCUITOS FPGA, EQUAÇÕES DIFERENCIAIS ORDINÁRIAS
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ABNT
SOUZA JUNIOR, Carlos Alberto Oliveira de. Applying Rosenbrock method for solving stiff ODEs raised from the chemical reactivity of the atmosphere through heterogeneous architectures based on FPGAs. 2023. Tese (Doutorado) – Universidade de São Paulo, São Carlos, 2023. Disponível em: https://www.teses.usp.br/teses/disponiveis/55/55134/tde-31082023-103217/. Acesso em: 17 jul. 2024.
APA
Souza Junior, C. A. O. de. (2023). Applying Rosenbrock method for solving stiff ODEs raised from the chemical reactivity of the atmosphere through heterogeneous architectures based on FPGAs (Tese (Doutorado). Universidade de São Paulo, São Carlos. Recuperado de https://www.teses.usp.br/teses/disponiveis/55/55134/tde-31082023-103217/
NLM
Souza Junior CAO de. Applying Rosenbrock method for solving stiff ODEs raised from the chemical reactivity of the atmosphere through heterogeneous architectures based on FPGAs [Internet]. 2023 ;[citado 2024 jul. 17 ] Available from: https://www.teses.usp.br/teses/disponiveis/55/55134/tde-31082023-103217/
Vancouver
Souza Junior CAO de. Applying Rosenbrock method for solving stiff ODEs raised from the chemical reactivity of the atmosphere through heterogeneous architectures based on FPGAs [Internet]. 2023 ;[citado 2024 jul. 17 ] Available from: https://www.teses.usp.br/teses/disponiveis/55/55134/tde-31082023-103217/
Trabalho de evento-anais periodico
Product development process for complex hardware-based solutions: current trends (2023)
Romeral, Pedro Antonio de Albuquerque Felizola ; Zancul, Eduardo de Senzi ; Nakano, Davi Noboru
Source: Procedia CIRP. Conference titles: CIRP Design Conference 2023. Unidade: EP
Subjects: DESENVOLVIMENTO DE PRODUTOS, HARDWARE, SERVIÇOS, DESIGN, REVISÃO SISTEMÁTICA
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ABNT
ROMERAL, Pedro Antonio de Albuquerque Felizola e ZANCUL, Eduardo de Senzi e NAKANO, Davi Noboru. Product development process for complex hardware-based solutions: current trends. Procedia CIRP. Amsterdam: Escola Politécnica, Universidade de São Paulo. Disponível em: https://doi.org/10.1016/j.procir.2023.03.133. Acesso em: 17 jul. 2024. , 2023
APA
Romeral, P. A. de A. F., Zancul, E. de S., & Nakano, D. N. (2023). Product development process for complex hardware-based solutions: current trends. Procedia CIRP. Amsterdam: Escola Politécnica, Universidade de São Paulo. doi:10.1016/j.procir.2023.03.133
NLM
Romeral PA de AF, Zancul E de S, Nakano DN. Product development process for complex hardware-based solutions: current trends [Internet]. Procedia CIRP. 2023 ; 119 885-890.[citado 2024 jul. 17 ] Available from: https://doi.org/10.1016/j.procir.2023.03.133
Vancouver
Romeral PA de AF, Zancul E de S, Nakano DN. Product development process for complex hardware-based solutions: current trends [Internet]. Procedia CIRP. 2023 ; 119 885-890.[citado 2024 jul. 17 ] Available from: https://doi.org/10.1016/j.procir.2023.03.133
Artigo de periodico
Class-specific early exit design methodology for convolutional neural networks (2021)
Bonato, Vanderlei ; Bouganis, Christos-Savvas
Source: Applied Soft Computing Journal. Unidade: ICMC
Subjects: HARDWARE, INFERÊNCIA, CONSUMO DE ENERGIA ELÉTRICA
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ABNT
BONATO, Vanderlei e BOUGANIS, Christos-Savvas. Class-specific early exit design methodology for convolutional neural networks. Applied Soft Computing Journal, v. 107, p. 1-12, 2021Tradução . . Disponível em: https://doi.org/10.1016/j.asoc.2021.107316. Acesso em: 17 jul. 2024.
APA
Bonato, V., & Bouganis, C. -S. (2021). Class-specific early exit design methodology for convolutional neural networks. Applied Soft Computing Journal, 107, 1-12. doi:10.1016/j.asoc.2021.107316
NLM
Bonato V, Bouganis C-S. Class-specific early exit design methodology for convolutional neural networks [Internet]. Applied Soft Computing Journal. 2021 ; 107 1-12.[citado 2024 jul. 17 ] Available from: https://doi.org/10.1016/j.asoc.2021.107316
Vancouver
Bonato V, Bouganis C-S. Class-specific early exit design methodology for convolutional neural networks [Internet]. Applied Soft Computing Journal. 2021 ; 107 1-12.[citado 2024 jul. 17 ] Available from: https://doi.org/10.1016/j.asoc.2021.107316
Artigo de periodico
Fast resource and timing aware design optimisation for high-level synthesis (2021)
Perina, André Bannwart ; Silitonga, Arthur ; Becker, Jürgen ; Bonato, Vanderlei
Source: IEEE Transactions on Computers. Unidade: ICMC
Subjects: HARDWARE, ANÁLISE DE DESEMPENHO
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ABNT
PERINA, André Bannwart et al. Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, v. 70, n. 12, p. 2070-2082, 2021Tradução . . Disponível em: https://doi.org/10.1109/TC.2021.3112260. Acesso em: 17 jul. 2024.
APA
Perina, A. B., Silitonga, A., Becker, J., & Bonato, V. (2021). Fast resource and timing aware design optimisation for high-level synthesis. IEEE Transactions on Computers, 70( 12), 2070-2082. doi:10.1109/TC.2021.3112260
NLM
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 jul. 17 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Vancouver
Perina AB, Silitonga A, Becker J, Bonato V. Fast resource and timing aware design optimisation for high-level synthesis [Internet]. IEEE Transactions on Computers. 2021 ; 70( 12): 2070-2082.[citado 2024 jul. 17 ] Available from: https://doi.org/10.1109/TC.2021.3112260
Artigo de periodico
Non-iterative SDC modulo scheduling for high-level synthesis (2021)
Rosa, Leandro de Souza ; Bouganis, Christos-Savvas ; Bonato, Vanderlei
Source: Microprocessors and Microsystems. Unidade: ICMC
Subjects: LAÇOS, HARDWARE, TEMPO
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ABNT
ROSA, Leandro de Souza e BOUGANIS, Christos-Savvas e BONATO, Vanderlei. Non-iterative SDC modulo scheduling for high-level synthesis. Microprocessors and Microsystems, v. 86, p. 1-13, 2021Tradução . . Disponível em: https://doi.org/10.1016/j.micpro.2021.104334. Acesso em: 17 jul. 2024.
APA
Rosa, L. de S., Bouganis, C. -S., & Bonato, V. (2021). Non-iterative SDC modulo scheduling for high-level synthesis. Microprocessors and Microsystems, 86, 1-13. doi:10.1016/j.micpro.2021.104334
NLM
Rosa L de S, Bouganis C-S, Bonato V. Non-iterative SDC modulo scheduling for high-level synthesis [Internet]. Microprocessors and Microsystems. 2021 ; 86 1-13.[citado 2024 jul. 17 ] Available from: https://doi.org/10.1016/j.micpro.2021.104334
Vancouver
Rosa L de S, Bouganis C-S, Bonato V. Non-iterative SDC modulo scheduling for high-level synthesis [Internet]. Microprocessors and Microsystems. 2021 ; 86 1-13.[citado 2024 jul. 17 ] Available from: https://doi.org/10.1016/j.micpro.2021.104334
Artigo de periodico
Exploration of FPGA-based hardware designs for QR decomposition for solving stiff ODE numerical methods using the HARP hybrid architecture (2020)
Souza Junior, Carlos Alberto Oliveira de ; Bispo, João ; Cardoso, João Manuel Paiva ; Diniz, Pedro C; Marques, Eduardo
Source: Electronics. Unidade: ICMC
Subjects: EQUAÇÕES DIFERENCIAIS ORDINÁRIAS, HARDWARE
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ABNT
SOUZA JUNIOR, Carlos Alberto Oliveira de et al. Exploration of FPGA-based hardware designs for QR decomposition for solving stiff ODE numerical methods using the HARP hybrid architecture. Electronics, v. 9, n. 5, p. 1-14, 2020Tradução . . Disponível em: https://doi.org/10.3390/electronics9050843. Acesso em: 17 jul. 2024.
APA
Souza Junior, C. A. O. de, Bispo, J., Cardoso, J. M. P., Diniz, P. C., & Marques, E. (2020). Exploration of FPGA-based hardware designs for QR decomposition for solving stiff ODE numerical methods using the HARP hybrid architecture. Electronics, 9( 5), 1-14. doi:10.3390/electronics9050843
NLM
Souza Junior CAO de, Bispo J, Cardoso JMP, Diniz PC, Marques E. Exploration of FPGA-based hardware designs for QR decomposition for solving stiff ODE numerical methods using the HARP hybrid architecture [Internet]. Electronics. 2020 ; 9( 5): 1-14.[citado 2024 jul. 17 ] Available from: https://doi.org/10.3390/electronics9050843
Vancouver
Souza Junior CAO de, Bispo J, Cardoso JMP, Diniz PC, Marques E. Exploration of FPGA-based hardware designs for QR decomposition for solving stiff ODE numerical methods using the HARP hybrid architecture [Internet]. Electronics. 2020 ; 9( 5): 1-14.[citado 2024 jul. 17 ] Available from: https://doi.org/10.3390/electronics9050843
Artigo de periodico
Operation of the ATLAS trigger system in Run 2 (2020)
Aad, G; Donadelli, Marisilvia ; Leite, Marco Aurelio Lisboa
Source: Journal of Instrumentation. Unidade: IF
Subjects: SOFTWARES, HARDWARE
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ABNT
AAD, G e DONADELLI, Marisilvia e LEITE, Marco Aurelio Lisboa. Operation of the ATLAS trigger system in Run 2. Journal of Instrumentation, v. 15, 2020Tradução . . Disponível em: https://doi.org/10.1088/1748-0221/15/10/P10004. Acesso em: 17 jul. 2024.
APA
Aad, G., Donadelli, M., & Leite, M. A. L. (2020). Operation of the ATLAS trigger system in Run 2. Journal of Instrumentation, 15. doi:10.1088/1748-0221/15/10/P10004
NLM
Aad G, Donadelli M, Leite MAL. Operation of the ATLAS trigger system in Run 2 [Internet]. Journal of Instrumentation. 2020 ; 15[citado 2024 jul. 17 ] Available from: https://doi.org/10.1088/1748-0221/15/10/P10004
Vancouver
Aad G, Donadelli M, Leite MAL. Operation of the ATLAS trigger system in Run 2 [Internet]. Journal of Instrumentation. 2020 ; 15[citado 2024 jul. 17 ] Available from: https://doi.org/10.1088/1748-0221/15/10/P10004
Tese (Doutorado)
Fast Code Exploration for Pipeline Processing in FPGA Accelerators (2019)
Rosa, Leandro de Souza; Bonato, Vanderlei (Orientador)
Unidade: ICMC
Subjects: CIRCUITOS FPGA, HARDWARE, COMPUTAÇÃO RECONFIGURÁVEL
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ABNT
ROSA, Leandro de Souza. Fast Code Exploration for Pipeline Processing in FPGA Accelerators. 2019. Tese (Doutorado) – Universidade de São Paulo, São Carlos, 2019. Disponível em: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-21082019-143417/. Acesso em: 17 jul. 2024.
APA
Rosa, L. de S. (2019). Fast Code Exploration for Pipeline Processing in FPGA Accelerators (Tese (Doutorado). Universidade de São Paulo, São Carlos. Recuperado de http://www.teses.usp.br/teses/disponiveis/55/55134/tde-21082019-143417/
NLM
Rosa L de S. Fast Code Exploration for Pipeline Processing in FPGA Accelerators [Internet]. 2019 ;[citado 2024 jul. 17 ] Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-21082019-143417/
Vancouver
Rosa L de S. Fast Code Exploration for Pipeline Processing in FPGA Accelerators [Internet]. 2019 ;[citado 2024 jul. 17 ] Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-21082019-143417/
Trabalho de evento
Low-cost hardware in the loop implementation of a boost converter (2019)
Castro, Daniel S.; Magossi, Rafael Fernando Quirino; Bastos, Renan Fernandes; Oliveira, Vilma Alves de ; Machado, Ricardo Quadros
Source: Proceedings. Conference titles: European Control Conference - ECC. Unidade: EESC
Subjects: CONVERSORES ELÉTRICOS, HARDWARE, ENGENHARIA ELÉTRICA
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ABNT
CASTRO, Daniel S. et al. Low-cost hardware in the loop implementation of a boost converter. 2019, Anais.. Piscataway, NJ, USA: Escola de Engenharia de São Carlos, Universidade de São Paulo, 2019. . Acesso em: 17 jul. 2024.
APA
Castro, D. S., Magossi, R. F. Q., Bastos, R. F., Oliveira, V. A. de, & Machado, R. Q. (2019). Low-cost hardware in the loop implementation of a boost converter. In Proceedings. Piscataway, NJ, USA: Escola de Engenharia de São Carlos, Universidade de São Paulo.
NLM
Castro DS, Magossi RFQ, Bastos RF, Oliveira VA de, Machado RQ. Low-cost hardware in the loop implementation of a boost converter. Proceedings. 2019 ;[citado 2024 jul. 17 ]
Vancouver
Castro DS, Magossi RFQ, Bastos RF, Oliveira VA de, Machado RQ. Low-cost hardware in the loop implementation of a boost converter. Proceedings. 2019 ;[citado 2024 jul. 17 ]
Trabalho de evento-resumo
ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis (2019)
Perina, André Bannwart ; Becker, Jürgen ; Bonato, Vanderlei
Source: Proceedings. Conference titles: IEEE International Conference on Electronics, Circuits and Systems - ICECS. Unidade: ICMC
Subjects: COMPUTAÇÃO RECONFIGURÁVEL, HARDWARE, MICROPROGRAMAÇÃO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis. 2019, Anais.. Los Alamitos: IEEE, 2019. Disponível em: https://doi.org/10.1109/ICECS46596.2019.8964669. Acesso em: 17 jul. 2024.
APA
Perina, A. B., Becker, J., & Bonato, V. (2019). ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis. In Proceedings. Los Alamitos: IEEE. doi:10.1109/ICECS46596.2019.8964669
NLM
Perina AB, Becker J, Bonato V. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis [Internet]. Proceedings. 2019 ;[citado 2024 jul. 17 ] Available from: https://doi.org/10.1109/ICECS46596.2019.8964669
Vancouver
Perina AB, Becker J, Bonato V. ProfCounter: line-level cycle counter for Xilinx OpenCL high-level synthesis [Internet]. Proceedings. 2019 ;[citado 2024 jul. 17 ] Available from: https://doi.org/10.1109/ICECS46596.2019.8964669
Trabalho de evento
Scaling up loop pipelining for high-level synthesis: a non-iterative approach (2018)
Rosa, Leandro de Souza ; Bonato, Vanderlei ; Bouganis, Christos-Savvas
Source: Proceedings. Conference titles: International Conference on Field-Programmable Technology - FPT. Unidade: ICMC
Subjects: HARDWARE, ANÁLISE DE DESEMPENHO
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROSA, Leandro de Souza e BONATO, Vanderlei e BOUGANIS, Christos-Savvas. Scaling up loop pipelining for high-level synthesis: a non-iterative approach. 2018, Anais.. Piscataway: IEEE, 2018. Disponível em: https://doi.org/10.1109/FPT.2018.00020. Acesso em: 17 jul. 2024.
APA
Rosa, L. de S., Bonato, V., & Bouganis, C. -S. (2018). Scaling up loop pipelining for high-level synthesis: a non-iterative approach. In Proceedings. Piscataway: IEEE. doi:10.1109/FPT.2018.00020
NLM
Rosa L de S, Bonato V, Bouganis C-S. Scaling up loop pipelining for high-level synthesis: a non-iterative approach [Internet]. Proceedings. 2018 ;[citado 2024 jul. 17 ] Available from: https://doi.org/10.1109/FPT.2018.00020
Vancouver
Rosa L de S, Bonato V, Bouganis C-S. Scaling up loop pipelining for high-level synthesis: a non-iterative approach [Internet]. Proceedings. 2018 ;[citado 2024 jul. 17 ] Available from: https://doi.org/10.1109/FPT.2018.00020

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