Dynamic function exchange in FPGA to redefine RISC-V multicore architectures at runtime (2025)
Alves, Téo Sobrino 
; Bonato, Vanderlei
Source: Lecture Notes in Computer Science - LNCS. Conference titles: International Symposium on Applied Reconfigurable Computing - ARC. Unidade: ICMC
Subjects: ARQUITETURA E ORGANIZAÇÃO DE COMPUTADORES, HARDWARE
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ALVES, Téo Sobrino e BONATO, Vanderlei. Dynamic function exchange in FPGA to redefine RISC-V multicore architectures at runtime. Lecture Notes in Computer Science - LNCS. Cham: Instituto de Ciências Matemáticas e de Computação, Universidade de São Paulo. Disponível em: https://doi.org/10.1007/978-3-031-87995-1_14. Acesso em: 17 jun. 2025. , 2025APA
Alves, T. S., & Bonato, V. (2025). Dynamic function exchange in FPGA to redefine RISC-V multicore architectures at runtime. Lecture Notes in Computer Science - LNCS. Cham: Instituto de Ciências Matemáticas e de Computação, Universidade de São Paulo. doi:10.1007/978-3-031-87995-1_14NLM
Alves TS, Bonato V. Dynamic function exchange in FPGA to redefine RISC-V multicore architectures at runtime [Internet]. Lecture Notes in Computer Science - LNCS. 2025 ; 15594 233-243.[citado 2025 jun. 17 ] Available from: https://doi.org/10.1007/978-3-031-87995-1_14Vancouver
Alves TS, Bonato V. Dynamic function exchange in FPGA to redefine RISC-V multicore architectures at runtime [Internet]. Lecture Notes in Computer Science - LNCS. 2025 ; 15594 233-243.[citado 2025 jun. 17 ] Available from: https://doi.org/10.1007/978-3-031-87995-1_14
