Lina: timing-constrained high-level synthesis performance estimator for fast DSE (2019)
Perina, André Bannwart 
; Becker, Jürgen ; Bonato, Vanderlei
Fonte: Proceedings. Nome do evento: International Conference on Field-Programmable Technology - ICFPT. Unidade: ICMC
Assuntos: CIRCUITOS FPGA, BENCHMARKS
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ABNT
PERINA, André Bannwart e BECKER, Jürgen e BONATO, Vanderlei. Lina: timing-constrained high-level synthesis performance estimator for fast DSE. 2019, Anais.. Los Alamitos: IEEE, 2019. Disponível em: https://doi.org/10.1109/ICFPT47387.2019.00063. Acesso em: 30 jun. 2025.APA
Perina, A. B., Becker, J., & Bonato, V. (2019). Lina: timing-constrained high-level synthesis performance estimator for fast DSE. In Proceedings. Los Alamitos: IEEE. doi:10.1109/ICFPT47387.2019.00063NLM
Perina AB, Becker J, Bonato V. Lina: timing-constrained high-level synthesis performance estimator for fast DSE [Internet]. Proceedings. 2019 ;[citado 2025 jun. 30 ] Available from: https://doi.org/10.1109/ICFPT47387.2019.00063Vancouver
Perina AB, Becker J, Bonato V. Lina: timing-constrained high-level synthesis performance estimator for fast DSE [Internet]. Proceedings. 2019 ;[citado 2025 jun. 30 ] Available from: https://doi.org/10.1109/ICFPT47387.2019.00063
