Synchronous state analysis for a master-slave clock distribution architecture (2003)
Piqueira, José Roberto Castilho 
; Vargas, Santos Andrés Castilho
Source: WSEAS Transactions on Circuits and Systems,. Unidade: EP
Subjects: SISTEMAS DINÂMICOS, TELECOMUNICAÇÕES
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PIQUEIRA, José Roberto Castilho e VARGAS, Santos Andrés Castilho. Synchronous state analysis for a master-slave clock distribution architecture. WSEAS Transactions on Circuits and Systems, v. 2, n. 2, p. 409-413, 2003Tradução . . Acesso em: 11 nov. 2025.APA
Piqueira, J. R. C., & Vargas, S. A. C. (2003). Synchronous state analysis for a master-slave clock distribution architecture. WSEAS Transactions on Circuits and Systems,, 2( 2), 409-413.NLM
Piqueira JRC, Vargas SAC. Synchronous state analysis for a master-slave clock distribution architecture. WSEAS Transactions on Circuits and Systems,. 2003 ; 2( 2): 409-413.[citado 2025 nov. 11 ]Vancouver
Piqueira JRC, Vargas SAC. Synchronous state analysis for a master-slave clock distribution architecture. WSEAS Transactions on Circuits and Systems,. 2003 ; 2( 2): 409-413.[citado 2025 nov. 11 ]
