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Trabalho de evento
Temperature influence on nanowire tunnel field effect transistors (2012)
Neves, Felipe Souza; Martino, Márcio Dalla Valle; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Rooyackers, Rita ; Leonelli, Daniele ; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
NEVES, Felipe Souza et al. Temperature influence on nanowire tunnel field effect transistors. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0223ecst. Acesso em: 29 maio 2024.
APA
Neves, F. S., Martino, M. D. V., Agopian, P. G. D., Martino, J. A., Rooyackers, R., Leonelli, D., & Claeys, C. (2012). Temperature influence on nanowire tunnel field effect transistors. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0223ecst
NLM
Neves FS, Martino MDV, Agopian PGD, Martino JA, Rooyackers R, Leonelli D, Claeys C. Temperature influence on nanowire tunnel field effect transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0223ecst
Vancouver
Neves FS, Martino MDV, Agopian PGD, Martino JA, Rooyackers R, Leonelli D, Claeys C. Temperature influence on nanowire tunnel field effect transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0223ecst
Trabalho de evento
Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors (2012)
Trevisoli, Renan ; Doria, Rodrigo Trevisoli ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
TREVISOLI, Renan et al. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0207ecst. Acesso em: 29 maio 2024.
APA
Trevisoli, R., Doria, R. T., Souza, M. de, & Pavanello, M. A. (2012). Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0207ecst
NLM
Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0207ecst
Vancouver
Trevisoli R, Doria RT, Souza M de, Pavanello MA. Accounting for short channel effects in the drain current modeling of junctionless nanowire transistors [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0207ecst
Trabalho de evento
Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements (2012)
Mariniello, Genaro ; Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
MARINIELLO, Genaro et al. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0231ecst. Acesso em: 29 maio 2024.
APA
Mariniello, G., Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0231ecst
NLM
Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0231ecst
Vancouver
Mariniello G, Doria RT, Trevisoli R, Souza M de, Pavanello MA. Intrinsic gate capacitances of n-type junctionless nanowire transistors using a three-dimensional device simulation and experimental measurements [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0231ecst
Trabalho de evento
On the variability of the low-frequency noise in UTBOX SOI nMOSFETs (2012)
Simoen, Eddy ; Caño de Andrade, Maria Glória ; Almeida, Luciano Mendes; Aoulaiche, Marc; Caillat, Christian; Jurczak, Malgorzata; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SIMOEN, Eddy et al. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0051ecst. Acesso em: 29 maio 2024.
APA
Simoen, E., Caño de Andrade, M. G., Almeida, L. M., Aoulaiche, M., Caillat, C., Jurczak, M., & Claeys, C. (2012). On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0051ecst
NLM
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0051ecst
Vancouver
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0051ecst
Trabalho de evento
Liquid helium temperature operation of graded-channel SOI nMOSFETs (2012)
Souza, Michelly de ; Kilchytska, Valeriya ; Flandre, Denis ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SOUZA, Michelly de et al. Liquid helium temperature operation of graded-channel SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0135ecst. Acesso em: 29 maio 2024.
APA
Souza, M. de, Kilchytska, V., Flandre, D., & Pavanello, M. A. (2012). Liquid helium temperature operation of graded-channel SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0135ecst
NLM
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0135ecst
Vancouver
Souza M de, Kilchytska V, Flandre D, Pavanello MA. Liquid helium temperature operation of graded-channel SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0135ecst
Trabalho de evento
Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI (2012)
Caño de Andrade, Maria Glória ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CAÑO DE ANDRADE, Maria Glória et al. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0111ecst. Acesso em: 29 maio 2024.
APA
Caño de Andrade, M. G., Martino, J. A., Simoen, E., & Claeys, C. (2012). Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0111ecst
NLM
Caño de Andrade MG, Martino JA, Simoen E, Claeys C. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0111ecst
Vancouver
Caño de Andrade MG, Martino JA, Simoen E, Claeys C. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0111ecst
Trabalho de evento
Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS (2012)
Santos, Sara Dereste dos ; Nicoletti, Talitha; Aoulaiche, Marc; Martino, João Antonio ; Veloso, A; Jurczak, Malgorzata; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SANTOS, Sara Dereste dos et al. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf. Acesso em: 29 maio 2024.
APA
Santos, S. D. dos, Nicoletti, T., Aoulaiche, M., Martino, J. A., Veloso, A., Jurczak, M., et al. (2012). Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. Recuperado de https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
NLM
Santos SD dos, Nicoletti T, Aoulaiche M, Martino JA, Veloso A, Jurczak M, Simoen E, Claeys C. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
Vancouver
Santos SD dos, Nicoletti T, Aoulaiche M, Martino JA, Veloso A, Jurczak M, Simoen E, Claeys C. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
Trabalho de evento
Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance (2012)
Doria, Rodrigo Trevisoli ; Trevisoli, Renan ; Souza, Michelly de ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
DORIA, Rodrigo Trevisoli et al. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0215ecst. Acesso em: 29 maio 2024.
APA
Doria, R. T., Trevisoli, R., Souza, M. de, & Pavanello, M. A. (2012). Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0215ecst
NLM
Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0215ecst
Vancouver
Doria RT, Trevisoli R, Souza M de, Pavanello MA. Application of junctionless nanowire transistor in the self-cascode configuration to improve the analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0215ecst
Trabalho de evento
Simulation of PECVD SiO2 deposition using a cellular automata approach (2012)
Colombo, Fábio Belotti; Páez Carreño, Marcelo Nelson
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
COLOMBO, Fábio Belotti e PÁEZ CARREÑO, Marcelo Nelson. Simulation of PECVD SiO2 deposition using a cellular automata approach. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0297ecst. Acesso em: 29 maio 2024.
APA
Colombo, F. B., & Páez Carreño, M. N. (2012). Simulation of PECVD SiO2 deposition using a cellular automata approach. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0297ecst
NLM
Colombo FB, Páez Carreño MN. Simulation of PECVD SiO2 deposition using a cellular automata approach [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0297ecst
Vancouver
Colombo FB, Páez Carreño MN. Simulation of PECVD SiO2 deposition using a cellular automata approach [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0297ecst
Trabalho de evento
Fabrication of transparent conductive thin films based on multi-walled carbon nanotubes (2012)
Abe, Igor Yamamoto ; Pereyra, Inés
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
ABE, Igor Yamamoto e PEREYRA, Inés. Fabrication of transparent conductive thin films based on multi-walled carbon nanotubes. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0255ecst. Acesso em: 29 maio 2024.
APA
Abe, I. Y., & Pereyra, I. (2012). Fabrication of transparent conductive thin films based on multi-walled carbon nanotubes. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0255ecst
NLM
Abe IY, Pereyra I. Fabrication of transparent conductive thin films based on multi-walled carbon nanotubes [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0255ecst
Vancouver
Abe IY, Pereyra I. Fabrication of transparent conductive thin films based on multi-walled carbon nanotubes [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0255ecst
Trabalho de evento
Impact of the extension region concentration on the UTBOX IT-FBRAM (2012)
Sasaki, Kátia Regina Akemi ; Almeida, L. M.; Martino, João Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SASAKI, Kátia Regina Akemi e ALMEIDA, L. M. e MARTINO, João Antonio. Impact of the extension region concentration on the UTBOX IT-FBRAM. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0281ecst. Acesso em: 29 maio 2024.
APA
Sasaki, K. R. A., Almeida, L. M., & Martino, J. A. (2012). Impact of the extension region concentration on the UTBOX IT-FBRAM. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0281ecst
NLM
Sasaki KRA, Almeida LM, Martino JA. Impact of the extension region concentration on the UTBOX IT-FBRAM [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0281ecst
Vancouver
Sasaki KRA, Almeida LM, Martino JA. Impact of the extension region concentration on the UTBOX IT-FBRAM [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0281ecst
Trabalho de evento
UTBOX SOI devices with high-k gate dielectric under analog performance (2012)
Galeti, Milene; Rodrigues, Michele; Aoulaiche, Marc; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
GALETI, Milene et al. UTBOX SOI devices with high-k gate dielectric under analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0119ecst. Acesso em: 29 maio 2024.
APA
Galeti, M., Rodrigues, M., Aoulaiche, M., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2012). UTBOX SOI devices with high-k gate dielectric under analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0119ecst
NLM
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0119ecst
Vancouver
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 maio 29 ] Available from: https://doi.org/10.1149/04901.0119ecst

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