ReP USP - Resultado da busca

Trabalho de evento
Temperature influences on the drain leakage current behavior in graded-channel SOI nMOSFETs (2005)
Bellodi, Marcello; Martino, João Antonio
Source: Microelectronics Technology and Devices SBMICRO 2005. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BELLODI, Marcello e MARTINO, João Antonio. Temperature influences on the drain leakage current behavior in graded-channel SOI nMOSFETs. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 06 jun. 2024.
APA
Bellodi, M., & Martino, J. A. (2005). Temperature influences on the drain leakage current behavior in graded-channel SOI nMOSFETs. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Bellodi M, Martino JA. Temperature influences on the drain leakage current behavior in graded-channel SOI nMOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Vancouver
Bellodi M, Martino JA. Temperature influences on the drain leakage current behavior in graded-channel SOI nMOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Trabalho de evento
Analysis of the linear kink effect in partially depleted SOI nMOSFETs (2005)
Agopian, Paula Ghedini Der ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics Technology and Devices SBMICRO 2005. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
AGOPIAN, Paula Ghedini Der et al. Analysis of the linear kink effect in partially depleted SOI nMOSFETs. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 06 jun. 2024.
APA
Agopian, P. G. D., Martino, J. A., Simoen, E., & Claeys, C. (2005). Analysis of the linear kink effect in partially depleted SOI nMOSFETs. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Agopian PGD, Martino JA, Simoen E, Claeys C. Analysis of the linear kink effect in partially depleted SOI nMOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Vancouver
Agopian PGD, Martino JA, Simoen E, Claeys C. Analysis of the linear kink effect in partially depleted SOI nMOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Trabalho de evento
Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K (2005)
Pavanello, Marcelo Antonio ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics Technology and Devices SBMICRO 2005. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 06 jun. 2024.
APA
Pavanello, M. A., Martino, J. A., Simoen, E., & Claeys, C. (2005). Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Martino JA, Simoen E, Claeys C. Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Vancouver
Pavanello MA, Martino JA, Simoen E, Claeys C. Comparison between bulk and floating body partially depleted SOI nMOSFETs for high frequency analog applications operating from 300 K down to 95 K. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Trabalho de evento
Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET (2005)
Paiola, A.G.; Nicolett, Aparecido Sirley; Martino, João Antonio
Source: Microelectronics Technology and Devices SBMICRO 2005. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAIOLA, A.G. e NICOLETT, Aparecido Sirley e MARTINO, João Antonio. Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 06 jun. 2024.
APA
Paiola, A. G., Nicolett, A. S., & Martino, J. A. (2005). Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Paiola AG, Nicolett AS, Martino JA. Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Vancouver
Paiola AG, Nicolett AS, Martino JA. Influence of the gate oxide tunneling effect on the extraction of the silicon film and front oxide thickness in SOI nMOSFET. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Trabalho de evento
A study of total series resistance and effective channel length comparing SOI nMOSFET and GC SOI nMOSFET in saturation region (2005)
Almeida, Galba Falce de; Martino, João Antonio
Source: Microelectronics Technology and Devices SBMICRO 2005. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ALMEIDA, Galba Falce de e MARTINO, João Antonio. A study of total series resistance and effective channel length comparing SOI nMOSFET and GC SOI nMOSFET in saturation region. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 06 jun. 2024.
APA
Almeida, G. F. de, & Martino, J. A. (2005). A study of total series resistance and effective channel length comparing SOI nMOSFET and GC SOI nMOSFET in saturation region. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Almeida GF de, Martino JA. A study of total series resistance and effective channel length comparing SOI nMOSFET and GC SOI nMOSFET in saturation region. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Vancouver
Almeida GF de, Martino JA. A study of total series resistance and effective channel length comparing SOI nMOSFET and GC SOI nMOSFET in saturation region. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Trabalho de evento
A simple method to model nonrectangular-gate layout in SOI MOSFETs (2005)
Giacomini, Renato Camargo; Martino, João Antonio
Source: Microelectronics Technology and Devices SBMICRO 2005. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GIACOMINI, Renato Camargo e MARTINO, João Antonio. A simple method to model nonrectangular-gate layout in SOI MOSFETs. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 06 jun. 2024.
APA
Giacomini, R. C., & Martino, J. A. (2005). A simple method to model nonrectangular-gate layout in SOI MOSFETs. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Giacomini RC, Martino JA. A simple method to model nonrectangular-gate layout in SOI MOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Vancouver
Giacomini RC, Martino JA. A simple method to model nonrectangular-gate layout in SOI MOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Trabalho de evento
Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments (2005)
Pavanello, Marcelo Antonio ; Cerdeira, Antonio ; Martino, João Antonio ; Alemán, Miguel A; Flandre, Denis
Source: Microelectronics Technology and Devices SBMICRO 2005. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 06 jun. 2024.
APA
Pavanello, M. A., Cerdeira, A., Martino, J. A., Alemán, M. A., & Flandre, D. (2005). Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Vancouver
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Trabalho de evento
Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range (2005)
Gimenez, Salvador Pinillos ; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis
Source: Microelectronics Technology and Devices SBMICRO 2005. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GIMENEZ, Salvador Pinillos et al. Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 06 jun. 2024.
APA
Gimenez, S. P., Pavanello, M. A., Martino, J. A., & Flandre, D. (2005). Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Gimenez SP, Pavanello MA, Martino JA, Flandre D. Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Vancouver
Gimenez SP, Pavanello MA, Martino JA, Flandre D. Potential of improved gain in operational transconductance amplifier using 0,5 Mm graded-channel SOI nMOSFET for applications in the gigahertz range. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Trabalho de evento
Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMOSFETs (2005)
Galeti, Milene; Claeys, Cor ; Martino, João Antonio ; Simoen, Eddy
Source: Microelectronics Technology and Devices SBMICRO 2005. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GALETI, Milene et al. Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMOSFETs. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 06 jun. 2024.
APA
Galeti, M., Claeys, C., Martino, J. A., & Simoen, E. (2005). Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMOSFETs. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Galeti M, Claeys C, Martino JA, Simoen E. Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]
Vancouver
Galeti M, Claeys C, Martino JA, Simoen E. Temperature and oxide thickness influence on the generation lifetime determination in partially depleted SOI nMOSFETs. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 jun. 06 ]

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