ReP USP - Resultado da busca

Trabalho de evento
Simulation of a Miller OpAmp with FinFETs at High temperatures (2012)
Contreras, Esteban ; Cerdeira, Antonio ; Pavanello, Marcelo Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CONTRERAS, Esteban e CERDEIRA, Antonio e PAVANELLO, Marcelo Antonio. Simulation of a Miller OpAmp with FinFETs at High temperatures. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0177ecst. Acesso em: 02 nov. 2024.
APA
Contreras, E., Cerdeira, A., & Pavanello, M. A. (2012). Simulation of a Miller OpAmp with FinFETs at High temperatures. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0177ecst
NLM
Contreras E, Cerdeira A, Pavanello MA. Simulation of a Miller OpAmp with FinFETs at High temperatures [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0177ecst
Vancouver
Contreras E, Cerdeira A, Pavanello MA. Simulation of a Miller OpAmp with FinFETs at High temperatures [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 nov. 02 ] Available from: https://doi.org/10.1149/04901.0177ecst
Parte de monografia/livro
Low temperature and channel engineering influence on harmonic distortion of soi nmosfets for analog applications (2005)
Pavanello, Marcelo Antonio ; Cerdeira, Antonio ; Alemán, Miguel A; Martino, João Antonio ; Vancaillie, Laurent; Flandre, Denis
Source: International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Conference titles: International Symposium on Silicon-on-Insulator Technology and Devices. Unidade: EP
Subjects: MICROELETRÔNICA, CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Low temperature and channel engineering influence on harmonic distortion of soi nmosfets for analog applications. International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Tradução . Pennington: The Electrochemical Society, 2005. . . Acesso em: 02 nov. 2024.
APA
Pavanello, M. A., Cerdeira, A., Alemán, M. A., Martino, J. A., Vancaillie, L., & Flandre, D. (2005). Low temperature and channel engineering influence on harmonic distortion of soi nmosfets for analog applications. In International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Cerdeira A, Alemán MA, Martino JA, Vancaillie L, Flandre D. Low temperature and channel engineering influence on harmonic distortion of soi nmosfets for analog applications. In: International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Pennington: The Electrochemical Society; 2005. [citado 2024 nov. 02 ]
Vancouver
Pavanello MA, Cerdeira A, Alemán MA, Martino JA, Vancaillie L, Flandre D. Low temperature and channel engineering influence on harmonic distortion of soi nmosfets for analog applications. In: International Symposium on Silicon-on-Insulator Technology and Devices XII: proceedings. Pennington: The Electrochemical Society; 2005. [citado 2024 nov. 02 ]
Trabalho de evento
Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments (2005)
Pavanello, Marcelo Antonio ; Cerdeira, Antonio ; Martino, João Antonio ; Alemán, Miguel A; Flandre, Denis
Source: Microelectronics Technology and Devices SBMICRO 2005. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. 2005, Anais.. Pennington: The Electrochemical Society, 2005. . Acesso em: 02 nov. 2024.
APA
Pavanello, M. A., Cerdeira, A., Martino, J. A., Alemán, M. A., & Flandre, D. (2005). Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. In Microelectronics Technology and Devices SBMICRO 2005. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 nov. 02 ]
Vancouver
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Implementation of tunable resistors using graded-channel SOI MOSFETs operating in cryogenic environments. Microelectronics Technology and Devices SBMICRO 2005. 2005 ;[citado 2024 nov. 02 ]
Artigo de periodico
Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor (2005)
Cerdeira, Antonio ; Alemán, Miguel A.; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Flandre, Denis ; Vancaillie, Laurent
Source: IEEE Transactions on Electron Devices. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CERDEIRA, Antonio et al. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, v. 52, n. 5, p. 967-972, 2005Tradução . . Disponível em: https://doi.org/10.1109/ted.2005.846327. Acesso em: 02 nov. 2024.
APA
Cerdeira, A., Alemán, M. A., Pavanello, M. A., Martino, J. A., Flandre, D., & Vancaillie, L. (2005). Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor. IEEE Transactions on Electron Devices, 52( 5), 967-972. doi:10.1109/ted.2005.846327
NLM
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2024 nov. 02 ] Available from: https://doi.org/10.1109/ted.2005.846327
Vancouver
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Flandre D, Vancaillie L. Advantages of the graded-channel SOI FD MOSFET for application as a quasi-linear resistor [Internet]. IEEE Transactions on Electron Devices. 2005 ;52( 5): 967-972.[citado 2024 nov. 02 ] Available from: https://doi.org/10.1109/ted.2005.846327
Trabalho de evento
Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures (2004)
Pavanello, Marcelo Antonio ; Cerdeira, Antonio ; Martino, João Antonio ; Alemán, Miguel A; Flandre, Denis
Source: Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. Conference titles: International Symposium on Microelectronics Technology and Devices SBMICRO. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PAVANELLO, Marcelo Antonio et al. Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. 2004, Anais.. Pennington: The Electrochemical Society, 2004. . Acesso em: 02 nov. 2024.
APA
Pavanello, M. A., Cerdeira, A., Martino, J. A., Alemán, M. A., & Flandre, D. (2004). Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. In Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. Pennington: The Electrochemical Society.
NLM
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2024 nov. 02 ]
Vancouver
Pavanello MA, Cerdeira A, Martino JA, Alemán MA, Flandre D. Analysis of harmonic distortion in graded-channel SOI MOSFETs at high temperatures. Microelectronic technology and devices SBMicro 2004. Proceedings, v. 2004-03. 2004 ;[citado 2024 nov. 02 ]
Trabalho de evento
On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET (2004)
Cerdeira, Antonio ; Alemán, Miguel A; Pavanello, Marcelo Antonio ; Martino, João Antonio ; Vancaillie, Laurent; Flandre, Denis
Source: ICCDCS 2004. Conference titles: IEEE International Caracas Conference on Devices, Circuits and Systems. Unidade: EP
Subjects: TRANSISTORES, CIRCUITOS INTEGRADOS MOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
CERDEIRA, Antonio et al. On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. 2004, Anais.. New York: IEEE, 2004. . Acesso em: 02 nov. 2024.
APA
Cerdeira, A., Alemán, M. A., Pavanello, M. A., Martino, J. A., Vancaillie, L., & Flandre, D. (2004). On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. In ICCDCS 2004. New York: IEEE.
NLM
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Vancaillie L, Flandre D. On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. ICCDCS 2004. 2004 ;[citado 2024 nov. 02 ]
Vancouver
Cerdeira A, Alemán MA, Pavanello MA, Martino JA, Vancaillie L, Flandre D. On-Resistance and harmonic distortion in graded-channel SOI FD MOSFET. ICCDCS 2004. 2004 ;[citado 2024 nov. 02 ]

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