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  • Source: Applied Soft Computing Journal. Unidade: ICMC

    Subjects: HARDWARE, INFERÊNCIA, CONSUMO DE ENERGIA ELÉTRICA

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    • ABNT

      BONATO, Vanderlei e BOUGANIS, Christos-Savvas. Class-specific early exit design methodology for convolutional neural networks. Applied Soft Computing Journal, v. 107, p. 1-12, 2021Tradução . . Disponível em: https://doi.org/10.1016/j.asoc.2021.107316. Acesso em: 03 jun. 2024.
    • APA

      Bonato, V., & Bouganis, C. -S. (2021). Class-specific early exit design methodology for convolutional neural networks. Applied Soft Computing Journal, 107, 1-12. doi:10.1016/j.asoc.2021.107316
    • NLM

      Bonato V, Bouganis C-S. Class-specific early exit design methodology for convolutional neural networks [Internet]. Applied Soft Computing Journal. 2021 ; 107 1-12.[citado 2024 jun. 03 ] Available from: https://doi.org/10.1016/j.asoc.2021.107316
    • Vancouver

      Bonato V, Bouganis C-S. Class-specific early exit design methodology for convolutional neural networks [Internet]. Applied Soft Computing Journal. 2021 ; 107 1-12.[citado 2024 jun. 03 ] Available from: https://doi.org/10.1016/j.asoc.2021.107316
  • Source: Microprocessors and Microsystems. Unidade: ICMC

    Subjects: LAÇOS, HARDWARE, TEMPO

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    • ABNT

      ROSA, Leandro de Souza e BOUGANIS, Christos-Savvas e BONATO, Vanderlei. Non-iterative SDC modulo scheduling for high-level synthesis. Microprocessors and Microsystems, v. 86, p. 1-13, 2021Tradução . . Disponível em: https://doi.org/10.1016/j.micpro.2021.104334. Acesso em: 03 jun. 2024.
    • APA

      Rosa, L. de S., Bouganis, C. -S., & Bonato, V. (2021). Non-iterative SDC modulo scheduling for high-level synthesis. Microprocessors and Microsystems, 86, 1-13. doi:10.1016/j.micpro.2021.104334
    • NLM

      Rosa L de S, Bouganis C-S, Bonato V. Non-iterative SDC modulo scheduling for high-level synthesis [Internet]. Microprocessors and Microsystems. 2021 ; 86 1-13.[citado 2024 jun. 03 ] Available from: https://doi.org/10.1016/j.micpro.2021.104334
    • Vancouver

      Rosa L de S, Bouganis C-S, Bonato V. Non-iterative SDC modulo scheduling for high-level synthesis [Internet]. Microprocessors and Microsystems. 2021 ; 86 1-13.[citado 2024 jun. 03 ] Available from: https://doi.org/10.1016/j.micpro.2021.104334
  • Source: Proceedings. Conference titles: International Conference on Field-Programmable Technology - FPT. Unidade: ICMC

    Subjects: HARDWARE, ANÁLISE DE DESEMPENHO

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    • ABNT

      ROSA, Leandro de Souza e BONATO, Vanderlei e BOUGANIS, Christos-Savvas. Scaling up loop pipelining for high-level synthesis: a non-iterative approach. 2018, Anais.. Piscataway: IEEE, 2018. Disponível em: https://doi.org/10.1109/FPT.2018.00020. Acesso em: 03 jun. 2024.
    • APA

      Rosa, L. de S., Bonato, V., & Bouganis, C. -S. (2018). Scaling up loop pipelining for high-level synthesis: a non-iterative approach. In Proceedings. Piscataway: IEEE. doi:10.1109/FPT.2018.00020
    • NLM

      Rosa L de S, Bonato V, Bouganis C-S. Scaling up loop pipelining for high-level synthesis: a non-iterative approach [Internet]. Proceedings. 2018 ;[citado 2024 jun. 03 ] Available from: https://doi.org/10.1109/FPT.2018.00020
    • Vancouver

      Rosa L de S, Bonato V, Bouganis C-S. Scaling up loop pipelining for high-level synthesis: a non-iterative approach [Internet]. Proceedings. 2018 ;[citado 2024 jun. 03 ] Available from: https://doi.org/10.1109/FPT.2018.00020

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