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Artigo de periodico
Experimental study of MISHEMT from 450 K down to 200 K for analog applications (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, CIRCUITOS ANALÓGICOS, SEMICONDUTORES
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ABNT
PERINA, Welder Fernandes et al. Experimental study of MISHEMT from 450 K down to 200 K for analog applications. Solid State Electronics, v. 208, p. 1-4, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108742. Acesso em: 18 jun. 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Experimental study of MISHEMT from 450 K down to 200 K for analog applications. Solid State Electronics, 208, 1-4. doi:10.1016/j.sse.2023.108742
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450 K down to 200 K for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450 K down to 200 K for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Artigo de periodico
Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications (2023)
Silva, V C P; Martino, João Antonio ; Simoen, Eddy ; Veloso, Anabela; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, TEMPERATURA, NANOTECNOLOGIA, CIRCUITOS ANALÓGICOS, CIRCUITOS DIGITAIS
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ABNT
SILVA, V C P et al. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, v. 208, p. 1-5, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108729. Acesso em: 18 jun. 2024.
APA
Silva, V. C. P., Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2023). Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications. Solid State Electronics, 208, 1-5. doi:10.1016/j.sse.2023.108729
NLM
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2023.108729
Vancouver
Silva VCP, Martino JA, Simoen E, Veloso A, Agopian PGD. Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications [Internet]. Solid State Electronics. 2023 ;208 1-5.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2023.108729
Artigo de periodico
Experimental study of MISHEMT from 450k down to 200 k for analog applications (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, CIRCUITOS ANALÓGICOS, TEMPERATURA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
PERINA, Welder Fernandes et al. Experimental study of MISHEMT from 450k down to 200 k for analog applications. Solid State Electronics, v. 208, p. 1-4, 2023Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2023.108742. Acesso em: 18 jun. 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Experimental study of MISHEMT from 450k down to 200 k for analog applications. Solid State Electronics, 208, 1-4. doi:10.1016/j.sse.2023.108742
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450k down to 200 k for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Experimental study of MISHEMT from 450k down to 200 k for analog applications [Internet]. Solid State Electronics. 2023 ; 208 1-4.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2023.108742
Trabalho de evento
Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K (2023)
Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: SBMicro. Conference titles: Symposium on Microelectronics Technology and Devices. Unidade: EP
Subjects: TRANSISTORES, SEMICONDUTORES
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ABNT
PERINA, Welder Fernandes et al. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K. 2023, Anais.. [Piscataway, N.J.]: IEEE, 2023. Disponível em: https://doi.org/10.1109/SBMicro60499.2023.10302604. Acesso em: 18 jun. 2024.
APA
Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K. In SBMicro. [Piscataway, N.J.]: IEEE. doi:10.1109/SBMicro60499.2023.10302604
NLM
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K [Internet]. SBMicro. 2023 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302604
Vancouver
Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. Study of the effect of multiple conductions on threshold voltage in a MIS-HEMT from 450 K down to 200 K [Internet]. SBMicro. 2023 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1109/SBMicro60499.2023.10302604
Artigo de periodico
MISHEMT intrinsic voltage gain under multiple channel output characteristics (2023)
Canales, Bruno Godoy; Perina, Welder Fernandes; Martino, João Antonio ; Simoen, Eddy ; Peralagu, Uthayasankaran; Collaert, Nadine ; Agopian, Paula Ghedini Der
Source: Semiconductor Science and Technology. Unidade: EP
Subjects: TRANSISTORES, SEMICONDUTORES
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ABNT
CANALES, Bruno Godoy et al. MISHEMT intrinsic voltage gain under multiple channel output characteristics. Semiconductor Science and Technology, v. 38, n. 11, p. 1-6, 2023Tradução . . Disponível em: https://doi.org/10.1088/1361-6641/acfa1f. Acesso em: 18 jun. 2024.
APA
Canales, B. G., Perina, W. F., Martino, J. A., Simoen, E., Peralagu, U., Collaert, N., & Agopian, P. G. D. (2023). MISHEMT intrinsic voltage gain under multiple channel output characteristics. Semiconductor Science and Technology, 38( 11), 1-6. doi:10.1088/1361-6641/acfa1f
NLM
Canales BG, Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. MISHEMT intrinsic voltage gain under multiple channel output characteristics [Internet]. Semiconductor Science and Technology. 2023 ; 38( 11): 1-6.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1088/1361-6641/acfa1f
Vancouver
Canales BG, Perina WF, Martino JA, Simoen E, Peralagu U, Collaert N, Agopian PGD. MISHEMT intrinsic voltage gain under multiple channel output characteristics [Internet]. Semiconductor Science and Technology. 2023 ; 38( 11): 1-6.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1088/1361-6641/acfa1f
Artigo de periodico
Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C (2022)
Sousa, Julia Cristina Soares; Perina, Welder F; Rangel, Roberto; Simoen, Eddy ; Veloso, Anabela; Martino, João Antonio ; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: NANOTECNOLOGIA, CIRCUITOS ANALÓGICOS, TRANSISTORES
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ABNT
SOUSA, Julia Cristina Soares et al. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C. Solid State Electronics, v. 189, p. 1-9, 2022Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2022.108238. Acesso em: 18 jun. 2024.
APA
Sousa, J. C. S., Perina, W. F., Rangel, R., Simoen, E., Veloso, A., Martino, J. A., & Agopian, P. G. D. (2022). Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C. Solid State Electronics, 189, 1-9. doi:10.1016/j.sse.2022.108238
NLM
Sousa JCS, Perina WF, Rangel R, Simoen E, Veloso A, Martino JA, Agopian PGD. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C [Internet]. Solid State Electronics. 2022 ;189 1-9.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2022.108238
Vancouver
Sousa JCS, Perina WF, Rangel R, Simoen E, Veloso A, Martino JA, Agopian PGD. Design of operational transconductance amplifier with gate-all-around nanosheet MOSFET using experimental data from room temperature to 200°C [Internet]. Solid State Electronics. 2022 ;189 1-9.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2022.108238
Artigo de periodico
Signal to noise ratio in nanoscale bioFETs (2022)
Mori, Carlos Augusto Bergfeld; Martens, Koen; Simoen, Eddy ; Van Dorpe, Pol; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: Solid State Electronics. Unidade: EP
Subjects: NANOELETRÔNICA, DNA
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ABNT
MORI, Carlos Augusto Bergfeld et al. Signal to noise ratio in nanoscale bioFETs. Solid State Electronics, v. 194, p. 1-4, 2022Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2022.108358. Acesso em: 18 jun. 2024.
APA
Mori, C. A. B., Martens, K., Simoen, E., Van Dorpe, P., Agopian, P. G. D., & Martino, J. A. (2022). Signal to noise ratio in nanoscale bioFETs. Solid State Electronics, 194, 1-4. doi:10.1016/j.sse.2022.108358
NLM
Mori CAB, Martens K, Simoen E, Van Dorpe P, Agopian PGD, Martino JA. Signal to noise ratio in nanoscale bioFETs [Internet]. Solid State Electronics. 2022 ; 194 1-4.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2022.108358
Vancouver
Mori CAB, Martens K, Simoen E, Van Dorpe P, Agopian PGD, Martino JA. Signal to noise ratio in nanoscale bioFETs [Internet]. Solid State Electronics. 2022 ; 194 1-4.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2022.108358
Artigo de periodico
Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C (2022)
Silva, Vanessa Cristina Pereira da; Leal, João Vitor da Costa; Perina, Welder F; Martino, João Antonio ; Simoen, Eddy ; Veloso, A; Agopian, Paula Ghedini Der
Source: Journal of Integrated Circuits and Systems. Unidade: EP
Subjects: TRANSISTORES, NANOTECNOLOGIA, BAIXA TEMPERATURA
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ABNT
SILVA, Vanessa Cristina Pereira da et al. Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C. Journal of Integrated Circuits and Systems, v. 17, n. 1, p. 1-6, 2022Tradução . . Disponível em: https://doi.org/10.29292/jics.v17il.550. Acesso em: 18 jun. 2024.
APA
Silva, V. C. P. da, Leal, J. V. da C., Perina, W. F., Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2022). Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C. Journal of Integrated Circuits and Systems, 17( 1), 1-6. doi:10.29292/jics.v17i1.550
NLM
Silva VCP da, Leal JV da C, Perina WF, Martino JA, Simoen E, Veloso A, Agopian PGD. Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C [Internet]. Journal of Integrated Circuits and Systems. 2022 ;17( 1): 1-6.[citado 2024 jun. 18 ] Available from: https://doi.org/10.29292/jics.v17il.550
Vancouver
Silva VCP da, Leal JV da C, Perina WF, Martino JA, Simoen E, Veloso A, Agopian PGD. Experimental analysis of trade-off between transistor efficiency and unit gain frequency of nanosheet NMOSFET down to -100°C [Internet]. Journal of Integrated Circuits and Systems. 2022 ;17( 1): 1-6.[citado 2024 jun. 18 ] Available from: https://doi.org/10.29292/jics.v17il.550
Artigo de periodico
Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature (2022)
Silva, Vanessa Cristina Pereira da; Martino, João Antonio ; Simoen, Eddy ; Veloso, Anabela; Agopian, Paula Ghedini Der
Source: Solid State Electronics. Unidade: EP
Subjects: TRANSISTORES, ALTA TEMPERATURA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SILVA, Vanessa Cristina Pereira da et al. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature. Solid State Electronics, v. 191, p. 1-8, 2022Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2022.108267. Acesso em: 18 jun. 2024.
APA
Silva, V. C. P. da, Martino, J. A., Simoen, E., Veloso, A., & Agopian, P. G. D. (2022). Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature. Solid State Electronics, 191, 1-8. doi:10.1016/j.sse.2022.108267
NLM
Silva VCP da, Martino JA, Simoen E, Veloso A, Agopian PGD. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature [Internet]. Solid State Electronics. 2022 ;191 1-8.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2022.108267
Vancouver
Silva VCP da, Martino JA, Simoen E, Veloso A, Agopian PGD. Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature [Internet]. Solid State Electronics. 2022 ;191 1-8.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2022.108267
Artigo de periodico
The impact of the temperature on In0.53Ga0.47As nTFETs (2018)
Bordallo, Caio Cesar Mendes ; Mocuta, Dan; Collaert, Nadine ; Alian, A; Simoen, Eddy ; Claeys, Cor ; Agopian, Paula Ghedini Der ; Martino, João Antonio ; Rooyackers, Rita; Mols, Yannick; Van Dooren, A; Verhulst, Anne S; Lin, D
Source: Composants nanoélectroniques. Unidade: EP
Assunto: SEMICONDUTORES
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ABNT
BORDALLO, Caio Cesar Mendes et al. The impact of the temperature on In0.53Ga0.47As nTFETs. Composants nanoélectroniques, v. 18, n. 1, 2018Tradução . . Disponível em: https://doi.org/10.21494/iste.op.2018.0224. Acesso em: 18 jun. 2024.
APA
Bordallo, C. C. M., Mocuta, D., Collaert, N., Alian, A., Simoen, E., Claeys, C., et al. (2018). The impact of the temperature on In0.53Ga0.47As nTFETs. Composants nanoélectroniques, 18( 1). doi:10.21494/iste.op.2018.0224
NLM
Bordallo CCM, Mocuta D, Collaert N, Alian A, Simoen E, Claeys C, Agopian PGD, Martino JA, Rooyackers R, Mols Y, Van Dooren A, Verhulst AS, Lin D. The impact of the temperature on In0.53Ga0.47As nTFETs [Internet]. Composants nanoélectroniques. 2018 ;18( 1):[citado 2024 jun. 18 ] Available from: https://doi.org/10.21494/iste.op.2018.0224
Vancouver
Bordallo CCM, Mocuta D, Collaert N, Alian A, Simoen E, Claeys C, Agopian PGD, Martino JA, Rooyackers R, Mols Y, Van Dooren A, Verhulst AS, Lin D. The impact of the temperature on In0.53Ga0.47As nTFETs [Internet]. Composants nanoélectroniques. 2018 ;18( 1):[citado 2024 jun. 18 ] Available from: https://doi.org/10.21494/iste.op.2018.0224
Artigo de periodico
Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices (2013)
Agopian, Paula Ghedini Der ; Bordallo, Caio Cesar Mendes ; Simoen, Eddy ; Martino, João Antonio ; Claeys, Cor
Source: Solid-State Electronics Volume 90, December 2013, Pages 155-159. Unidade: EP
Subjects: SILÍCIO, IRRADIAÇÃO
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ABNT
AGOPIAN, Paula Ghedini Der et al. Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices. Solid-State Electronics Volume 90, December 2013, Pages 155-159, v. 90, p. 155-159, 2013Tradução . . Disponível em: https://doi.org/10.1016/j.sse.2013.02.037. Acesso em: 18 jun. 2024.
APA
Agopian, P. G. D., Bordallo, C. C. M., Simoen, E., Martino, J. A., & Claeys, C. (2013). Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices. Solid-State Electronics Volume 90, December 2013, Pages 155-159, 90, 155-159. doi:10.1016/j.sse.2013.02.037
NLM
Agopian PGD, Bordallo CCM, Simoen E, Martino JA, Claeys C. Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices [Internet]. Solid-State Electronics Volume 90, December 2013, Pages 155-159. 2013 ; 90 155-159.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2013.02.037
Vancouver
Agopian PGD, Bordallo CCM, Simoen E, Martino JA, Claeys C. Stress engineering and proton radiation influence on off-state leakage current in triple-gate SOI devices [Internet]. Solid-State Electronics Volume 90, December 2013, Pages 155-159. 2013 ; 90 155-159.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1016/j.sse.2013.02.037
Trabalho de evento
On the variability of the low-frequency noise in UTBOX SOI nMOSFETs (2012)
Simoen, Eddy ; Caño de Andrade, Maria Glória ; Almeida, Luciano Mendes; Aoulaiche, Marc; Caillat, Christian; Jurczak, Malgorzata; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SIMOEN, Eddy et al. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0051ecst. Acesso em: 18 jun. 2024.
APA
Simoen, E., Caño de Andrade, M. G., Almeida, L. M., Aoulaiche, M., Caillat, C., Jurczak, M., & Claeys, C. (2012). On the variability of the low-frequency noise in UTBOX SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0051ecst
NLM
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/04901.0051ecst
Vancouver
Simoen E, Caño de Andrade MG, Almeida LM, Aoulaiche M, Caillat C, Jurczak M, Claeys C. On the variability of the low-frequency noise in UTBOX SOI nMOSFETs [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/04901.0051ecst
Trabalho de evento
Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI (2012)
Caño de Andrade, Maria Glória ; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
CAÑO DE ANDRADE, Maria Glória et al. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0111ecst. Acesso em: 18 jun. 2024.
APA
Caño de Andrade, M. G., Martino, J. A., Simoen, E., & Claeys, C. (2012). Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0111ecst
NLM
Caño de Andrade MG, Martino JA, Simoen E, Claeys C. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/04901.0111ecst
Vancouver
Caño de Andrade MG, Martino JA, Simoen E, Claeys C. Analog performance at room and low temperature of triple-gate devices: Bulk, DTMOS, BOI and SOI [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/04901.0111ecst
Trabalho de evento
Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS (2012)
Santos, Sara Dereste dos ; Nicoletti, Talitha; Aoulaiche, Marc; Martino, João Antonio ; Veloso, A; Jurczak, Malgorzata; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
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ABNT
SANTOS, Sara Dereste dos et al. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf. Acesso em: 18 jun. 2024.
APA
Santos, S. D. dos, Nicoletti, T., Aoulaiche, M., Martino, J. A., Veloso, A., Jurczak, M., et al. (2012). Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. Recuperado de https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
NLM
Santos SD dos, Nicoletti T, Aoulaiche M, Martino JA, Veloso A, Jurczak M, Simoen E, Claeys C. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
Vancouver
Santos SD dos, Nicoletti T, Aoulaiche M, Martino JA, Veloso A, Jurczak M, Simoen E, Claeys C. Spacer length and tilt implantation influence on scaled UTBOX FD MOSFETS [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://repositorio.usp.br/directbitstream/22d2dffe-4364-4c9f-87ae-bbce2402e1e6/3144801.pdf
Trabalho de evento
Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. (2012)
Itocazu, Vitor Tatsuo ; Sonnenberg, Victor ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ITOCAZU, Vitor Tatsuo et al. Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0511ecst. Acesso em: 18 jun. 2024.
APA
Itocazu, V. T., Sonnenberg, V., Simoen, E., Claeys, C., & Martino, J. A. (2012). Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0511ecst
NLM
Itocazu VT, Sonnenberg V, Simoen E, Claeys C, Martino JA. Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/04901.0511ecst
Vancouver
Itocazu VT, Sonnenberg V, Simoen E, Claeys C, Martino JA. Analysis of the silicon film thickness and the ground plane influence on ultra thin buried oxide SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/04901.0511ecst
Trabalho de evento
Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. (2012)
Bühler, Rudolf Theoderich ; Agopian, Paula Ghedini Der ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BÜHLER, Rudolf Theoderich et al. Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0145ecst. Acesso em: 18 jun. 2024.
APA
Bühler, R. T., Agopian, P. G. D., Simoen, E., Claeys, C., & Martino, J. A. (2012). Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0145ecst
NLM
Bühler RT, Agopian PGD, Simoen E, Claeys C, Martino JA. Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/04901.0145ecst
Vancouver
Bühler RT, Agopian PGD, Simoen E, Claeys C, Martino JA. Biaxial stress simulation and electrical characterization of triple-gate SOI nMOSFETs. [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/04901.0145ecst
Trabalho de evento
UTBOX SOI devices with high-k gate dielectric under analog performance (2012)
Galeti, Milene; Rodrigues, Michele; Aoulaiche, Marc; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Microelectronics technology and devices, SBMicro. Conference titles: International Symposium on Microelectronics Technology and Devices. Unidade: EP
Assunto: MICROELETRÔNICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GALETI, Milene et al. UTBOX SOI devices with high-k gate dielectric under analog performance. 2012, Anais.. Pennington: Escola Politécnica, Universidade de São Paulo, 2012. Disponível em: https://doi.org/10.1149/04901.0119ecst. Acesso em: 18 jun. 2024.
APA
Galeti, M., Rodrigues, M., Aoulaiche, M., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2012). UTBOX SOI devices with high-k gate dielectric under analog performance. In Microelectronics technology and devices, SBMicro. Pennington: Escola Politécnica, Universidade de São Paulo. doi:10.1149/04901.0119ecst
NLM
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/04901.0119ecst
Vancouver
Galeti M, Rodrigues M, Aoulaiche M, Collaert N, Simoen E, Claeys C, Martino JA. UTBOX SOI devices with high-k gate dielectric under analog performance [Internet]. Microelectronics technology and devices, SBMicro. 2012 ;[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/04901.0119ecst
Artigo de periodico
DIBL behavior of triple gate FinFETs with SEG on biaxial strained devices (2010)
Santos, Sara Dereste dos ; Nicoletti, Talitha; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics Technology and Devices - SBMicro 2010. Unidade: EP
Assunto: DISPOSITIVOS ELETRÔNICOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
SANTOS, Sara Dereste dos et al. DIBL behavior of triple gate FinFETs with SEG on biaxial strained devices. Microelectronics Technology and Devices - SBMicro 2010, v. 31, n. 1, p. 51-58, 2010Tradução . . Disponível em: https://doi.org/10.1149/1.3474141. Acesso em: 18 jun. 2024.
APA
Santos, S. D. dos, Nicoletti, T., Martino, J. A., Simoen, E., & Claeys, C. (2010). DIBL behavior of triple gate FinFETs with SEG on biaxial strained devices. Microelectronics Technology and Devices - SBMicro 2010, 31( 1), 51-58. doi:10.1149/1.3474141
NLM
Santos SD dos, Nicoletti T, Martino JA, Simoen E, Claeys C. DIBL behavior of triple gate FinFETs with SEG on biaxial strained devices [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 51-58.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/1.3474141
Vancouver
Santos SD dos, Nicoletti T, Martino JA, Simoen E, Claeys C. DIBL behavior of triple gate FinFETs with SEG on biaxial strained devices [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 51-58.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/1.3474141
Artigo de periodico
Improved analytical model for ZTC bias point for strained Tri-gates FinFETs (2010)
Almeida, Luciano Mendes; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Microelectronics Technology and Devices - SBMicro 2010. Unidade: EP
Assunto: ELETROQUÍMICA
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ALMEIDA, Luciano Mendes et al. Improved analytical model for ZTC bias point for strained Tri-gates FinFETs. Microelectronics Technology and Devices - SBMicro 2010, v. 31, n. 1, p. 385-392, 2010Tradução . . Disponível em: https://doi.org/10.1149/1.3474183. Acesso em: 18 jun. 2024.
APA
Almeida, L. M., Martino, J. A., Simoen, E., & Claeys, C. (2010). Improved analytical model for ZTC bias point for strained Tri-gates FinFETs. Microelectronics Technology and Devices - SBMicro 2010, 31( 1), 385-392. doi:10.1149/1.3474183
NLM
Almeida LM, Martino JA, Simoen E, Claeys C. Improved analytical model for ZTC bias point for strained Tri-gates FinFETs [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 385-392.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/1.3474183
Vancouver
Almeida LM, Martino JA, Simoen E, Claeys C. Improved analytical model for ZTC bias point for strained Tri-gates FinFETs [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 385-392.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/1.3474183
Artigo de periodico
Analog performance of SOI nFinFETs with different TiN gate electrode thickness (2010)
Galeti, Milene; Rodrigues, Michele; Collaert, Nadine ; Simoen, Eddy ; Claeys, Cor ; Martino, João Antonio
Source: Microelectronics Technology and Devices - SBMicro 2010. Unidade: EP
Assunto: TRANSISTORES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
GALETI, Milene et al. Analog performance of SOI nFinFETs with different TiN gate electrode thickness. Microelectronics Technology and Devices - SBMicro 2010, v. 31, n. 1, p. 59-65, 2010Tradução . . Disponível em: https://doi.org/10.1149/1.3474142. Acesso em: 18 jun. 2024.
APA
Galeti, M., Rodrigues, M., Collaert, N., Simoen, E., Claeys, C., & Martino, J. A. (2010). Analog performance of SOI nFinFETs with different TiN gate electrode thickness. Microelectronics Technology and Devices - SBMicro 2010, 31( 1), 59-65. doi:10.1149/1.3474142
NLM
Galeti M, Rodrigues M, Collaert N, Simoen E, Claeys C, Martino JA. Analog performance of SOI nFinFETs with different TiN gate electrode thickness [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 59-65.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/1.3474142
Vancouver
Galeti M, Rodrigues M, Collaert N, Simoen E, Claeys C, Martino JA. Analog performance of SOI nFinFETs with different TiN gate electrode thickness [Internet]. Microelectronics Technology and Devices - SBMicro 2010. 2010 ;31( 1): 59-65.[citado 2024 jun. 18 ] Available from: https://doi.org/10.1149/1.3474142

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